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authorArthur Heymans <arthur@aheymans.xyz>2022-04-19 21:46:20 +0200
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-11-16 04:22:00 +0000
commitdf0968062622072fe87408c736b71dd4ab1f37fd (patch)
treee3e9426e171e2c7a12b67988624b2b6a423fdf8a /src/soc/amd
parentc429ee1d9764398fe9dbb3e34b03bd3bd6d95ed9 (diff)
soc/amd/picasso: Add support for 64bit builds
Tested on google/vilboz (running the PCI rom with yabel). Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/common/block/cpu/noncar/pre_c.S11
-rw-r--r--src/soc/amd/picasso/Kconfig1
-rw-r--r--src/soc/amd/picasso/Makefile.inc4
3 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 5c16c29c8f..503de3b5f4 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -25,6 +25,10 @@ bootblock_resume_entry:
bootblock_pre_c_entry:
post_code(0xa0)
+#if ENV_X86_64
+ #include <cpu/x86/64bit/entry64.inc>
+#endif
+
/* Clear .bss section */
cld
xor %eax, %eax
@@ -40,10 +44,17 @@ bootblock_pre_c_entry:
and $0xfffffff0, %esp
sub $8, %esp
+#if ENV_X86_64
+ movd %mm2, %rdi
+ shlq $32, %rdi
+ movd %mm1, %rsi
+ or %rsi, %rdi
+#else
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */
+#endif
post_code(0xa2)
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 7f56803f8e..765ac4c72f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI
+ select HAVE_EXP_X86_64_SUPPORT
config CHIPSET_DEVICETREE
string
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index ab18e3bc1d..504a40ef85 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -143,8 +143,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
# type = 0x62
PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
PSP_ELF_FILE=$(objcbfs)/bootblock.elf
-PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
-PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x63 - construct APOB NV base/size from flash map
# The flashmap section used for this is expected to be named RW_MRC_CACHE
APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h)