diff options
| author | Marc Jones <marc.jones@scarletltd.com> | 2018-03-31 22:46:57 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-09 09:41:47 +0000 |
| commit | d6a82007bdc441046225269c39b06e1816c01458 (patch) | |
| tree | db234b365894d7012643528d58a926153da90de8 /src/soc/amd | |
| parent | f126b4b8f8ddd061380515b60594c21d1c6c52dc (diff) | |
amd/stoneyridge: Add GNB IOAPIC init
Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.
BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.
Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c640c1f00c..a7c78e65b0 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -15,6 +15,7 @@ #include <arch/io.h> +#include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <cbmem.h> @@ -69,12 +70,20 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, static void read_resources(device_t dev) { + struct resource *res; + /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) @@ -165,6 +174,7 @@ static void set_resources(device_t dev) static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) |