aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
authorFelix Held <felix.held@amd.corp-partner.google.com>2021-10-20 20:18:12 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-10-21 20:51:43 +0000
commitd27ef5bf6f5e444141dca6a89c46e667bca64652 (patch)
tree5625401e34f2a4f08175023de22172e4fa95589e /src/soc/amd
parente0e49c858bc603ac8216cd3d87c6a4a9996a8083 (diff)
cpu/x86/mp_init: use cb_err as mp_init_with_smm return type
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/cpu.c3
-rw-r--r--src/soc/amd/picasso/cpu.c3
-rw-r--r--src/soc/amd/stoneyridge/cpu.c3
3 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 2ac30b6b9f..a2fa433a9b 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
+#include <types.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
@@ -51,7 +52,7 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
/* Clear for take-off */
- if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
printk(BIOS_ERR, "MP initialization failure.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index b04d004f59..087b153998 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -19,6 +19,7 @@
#include <soc/iomap.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
+#include <types.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
@@ -55,7 +56,7 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
/* Clear for take-off */
- if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
printk(BIOS_ERR, "MP initialization failure.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 9283ff76e0..08f553351c 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -18,6 +18,7 @@
#include <soc/smi.h>
#include <soc/iomap.h>
#include <console/console.h>
+#include <types.h>
/*
* MP and SMM loading initialization.
@@ -53,7 +54,7 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
/* Clear for take-off */
- if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
printk(BIOS_ERR, "MP initialization failure.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */