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| author | Varshit B Pandya <varshit.b.pandya@intel.com> | 2022-03-29 18:16:20 +0530 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-04-01 13:45:57 +0000 |
| commit | d025ab3bc2e2a9e116bfa43a3abf2f16ed4e7147 (patch) | |
| tree | 1607941ec0d99e3f725d4aef669f1076f1daa623 /src/soc/amd | |
| parent | e7d3a1a9e8e69cfa2963339e7cf45160509cd784 (diff) | |
soc/intel/alderlake: Add HID for DPTF Power Participant
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device HID
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions