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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-06 00:26:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:44:13 +0000 |
| commit | befec1e92ef3dca5e7e7cf8e5c8c465e22f68ea2 (patch) | |
| tree | 5cd5870755d12a8700a5f5475dc75889f9df3d56 /src/soc/amd | |
| parent | 4a08736242d04fab5b6db09a6118cd992e038f9e (diff) | |
soc/amd/common: add Kconfig help text to pre-family-17h-only blocks
The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.
Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/pi/Kconfig | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 5941599df0..f6756e18f8 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -8,3 +8,6 @@ config SOC_AMD_COMMON_BLOCK_CAR it may not be appropriate for a romstage implementation without additional consideration. If this option is not used, the SOC must implement these functions separately. + This is only used for AMD CPU before family 17h. From family 17h on + the RAM is already initialized by the PSP before the x86 cores are + released from reset. diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig index f0917bb767..cf8c79ae50 100644 --- a/src/soc/amd/common/block/pi/Kconfig +++ b/src/soc/amd/common/block/pi/Kconfig @@ -3,7 +3,8 @@ config SOC_AMD_COMMON_BLOCK_PI select HAVE_DEBUG_RAM_SETUP default n help - This option builds functions that interface AMD's AGESA. + This option builds functions that interface AMD's AGESA reference + code packaged in the binaryPI form. if SOC_AMD_COMMON_BLOCK_PI |