diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-02 10:32:03 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-04-05 15:02:00 +0000 |
| commit | b92383a8a5adc3be5a18477c559badad3de01af8 (patch) | |
| tree | 3856526c08d01f5ee1e01291f250044841c564aa /src/soc/amd | |
| parent | 1d0e4930baa5afabdb6d531bbae31a61da7c2f87 (diff) | |
soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c8309a5ceb..fe49fe802c 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -885,6 +885,11 @@ int espi_setup(void) uint32_t slave_caps; const struct espi_config *cfg = espi_get_config(); + espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN); + espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); + espi_write32(ESPI_SLAVE0_INT_EN, 0); + espi_clear_status(); + /* * Boot sequence: Step 1 * Set correct initial configuration to talk to the slave: @@ -962,5 +967,8 @@ int espi_setup(void) /* Enable subtractive decode if configured */ espi_setup_subtractive_decode(cfg); + espi_write32(ESPI_GLOBAL_CONTROL_1, + espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN); + return 0; } |