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authorKangheui Won <khwon@chromium.org>2021-05-07 17:12:41 +1000
committerMartin Roth <martinroth@google.com>2021-05-10 04:07:51 +0000
commita8779941dc27bee0bd24142ec87318e3ac3e9321 (patch)
tree337e8535a41762ac511d45ccc2da5e527df4368c /src/soc/amd
parentdad067f2729565eb1adcdf792c4d4dcc48909ad0 (diff)
cezanne/psp_verstage: update SRAM address
Loading address and size for the user app has been changed with recent PSP release. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/include/soc/psp_verstage_addr.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
index bdc46cb84e..569d6e1d50 100644
--- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
+++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
@@ -8,8 +8,8 @@
* header for the user app (verstage) must be mapped.
* Size is 0x14000 bytes
*/
-#define PSP_SRAM_START 0x36000
-#define PSP_SRAM_SIZE (80K)
+#define PSP_SRAM_START 0x26000
+#define PSP_SRAM_SIZE (148K)
#define VERSTAGE_START PSP_SRAM_START
/*
@@ -17,7 +17,7 @@
* and make the size a multiple of 4k
*/
-#define PSP_VERSTAGE_STACK_START 0x49000
-#define PSP_VERSTAGE_STACK_SIZE (4K)
+#define PSP_VERSTAGE_STACK_START 0x41000
+#define PSP_VERSTAGE_STACK_SIZE (40K)
#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */