soc/amd/*/include/data_fabric: reorder register definitions

Order the data fabric register definitions by function number and
register offset.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

5 files changed, 63 insertions, 64 deletions

diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h
index eac8801113..5aabc2308b 100644
--- a/src/soc/amd/cezanne/include/soc/data_fabric.h
+++ b/src/soc/amd/cezanne/include/soc/data_fabric.h
@@ -6,6 +6,8 @@
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
 
+#define IOMS0_FABRIC_ID			10
+
 #define DF_MMIO_BASE0			DF_REG_ID(0, 0x200)
 #define DF_MMIO_LIMIT0			DF_REG_ID(0, 0x204)
 #define   DF_MMIO_SHIFT			16
@@ -14,12 +16,6 @@
 #define DF_MMIO_REG_SET_SIZE		4
 #define DF_MMIO_REG_SET_COUNT		8
 
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
-#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
-
-#define IOMS0_FABRIC_ID			10
-
 union df_mmio_control {
 	struct {
 		uint32_t re        :  1; /* [ 0.. 0] */
@@ -33,6 +29,10 @@ union df_mmio_control {
 	uint32_t raw;
 };
 
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
+#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
+
 union df_ficaa {
 	struct {
 		uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */
diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h
index d34c4daeb1..9ebb74f96b 100644
--- a/src/soc/amd/glinda/include/soc/data_fabric.h
+++ b/src/soc/amd/glinda/include/soc/data_fabric.h
@@ -6,6 +6,8 @@
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
 
+#define IOMS0_FABRIC_ID			15
+
 #define DF_MMIO_BASE0			DF_REG_ID(0, 0xD80)
 #define DF_MMIO_LIMIT0			DF_REG_ID(0, 0xD84)
 #define   DF_MMIO_SHIFT			16
@@ -14,12 +16,6 @@
 #define DF_MMIO_REG_SET_SIZE		4
 #define DF_MMIO_REG_SET_COUNT		8
 
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
-#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
-
-#define IOMS0_FABRIC_ID			15
-
 union df_mmio_control {
 	struct {
 		uint32_t re        :  1; /* [ 0.. 0] */
@@ -33,6 +29,10 @@ union df_mmio_control {
 	uint32_t raw;
 };
 
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
+#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
+
 union df_ficaa {
 	struct {
 		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h
index c20f252b20..4a399eb34f 100644
--- a/src/soc/amd/mendocino/include/soc/data_fabric.h
+++ b/src/soc/amd/mendocino/include/soc/data_fabric.h
@@ -6,6 +6,8 @@
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
 
+#define IOMS0_FABRIC_ID			9
+
 #define DF_MMIO_BASE0			DF_REG_ID(0, 0x200)
 #define DF_MMIO_LIMIT0			DF_REG_ID(0, 0x204)
 #define   DF_MMIO_SHIFT			16
@@ -19,12 +21,6 @@
 
 #define DF_MMIO_REG_SET_COUNT		8
 
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
-#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
-
-#define IOMS0_FABRIC_ID			9
-
 union df_mmio_control {
 	struct {
 		uint32_t re        :  1; /* [ 0.. 0] */
@@ -38,6 +34,10 @@ union df_mmio_control {
 	uint32_t raw;
 };
 
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
+#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
+
 union df_ficaa {
 	struct {
 		uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */
diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h
index ccb830fee0..e950817cbe 100644
--- a/src/soc/amd/phoenix/include/soc/data_fabric.h
+++ b/src/soc/amd/phoenix/include/soc/data_fabric.h
@@ -6,6 +6,8 @@
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
 
+#define IOMS0_FABRIC_ID			0x13
+
 #define DF_MMIO_BASE0			DF_REG_ID(0, 0xD80)
 #define DF_MMIO_LIMIT0			DF_REG_ID(0, 0xD84)
 #define   DF_MMIO_SHIFT			16
@@ -14,12 +16,6 @@
 #define DF_MMIO_REG_SET_SIZE		4
 #define DF_MMIO_REG_SET_COUNT		8
 
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
-#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
-
-#define IOMS0_FABRIC_ID			0x13
-
 union df_mmio_control {
 	struct {
 		uint32_t re        :  1; /* [ 0.. 0] */
@@ -33,6 +29,10 @@ union df_mmio_control {
 	uint32_t raw;
 };
 
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
+#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
+
 union df_ficaa {
 	struct {
 		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h
index fe9d25a918..98648774e6 100644
--- a/src/soc/amd/picasso/include/soc/data_fabric.h
+++ b/src/soc/amd/picasso/include/soc/data_fabric.h
@@ -6,47 +6,8 @@
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
 
-#define DF_MMIO_BASE0			DF_REG_ID(0, 0x200)
-#define DF_MMIO_LIMIT0			DF_REG_ID(0, 0x204)
-#define   DF_MMIO_SHIFT			16
-#define DF_MMIO_CTRL0			DF_REG_ID(0, 0x208)
-
-#define DF_MMIO_REG_SET_SIZE		4
-#define DF_MMIO_REG_SET_COUNT		8
-
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
-#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
-
 #define IOMS0_FABRIC_ID			9
 
-union df_mmio_control {
-	struct {
-		uint32_t re        :  1; /* [ 0.. 0] */
-		uint32_t we        :  1; /* [ 1.. 1] */
-		uint32_t           :  2; /* [ 3.. 2] */
-		uint32_t fabric_id :  8; /* [11.. 4] */
-		uint32_t np        :  1; /* [12..12] */
-		uint32_t           : 19; /* [31..13] */
-	};
-	uint32_t raw;
-};
-
-union df_ficaa {
-	struct {
-		uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */
-		uint32_t                 : 1; /* [ 1.. 1] */
-		uint32_t reg_num         : 9; /* [10.. 2] */
-		uint32_t func_num        : 3; /* [13..11] */
-		uint32_t b64_en          : 1; /* [14..14] */
-		uint32_t                 : 1; /* [15..15] */
-		uint32_t inst_id         : 8; /* [23..16] */
-		uint32_t                 : 8; /* [31..24] */
-	};
-	uint32_t raw;
-};
-
-
 #define D18F0_VGAEN			DF_REG_ID(0, 0x80)
 #define   VGA_ADDR_ENABLE		BIT(0)
 
@@ -55,7 +16,7 @@ union df_ficaa {
 #define   DRAM_HOLE_CTL_BASE_SHFT	24
 #define   DRAM_HOLE_CTL_BASE		(0xff << DRAM_HOLE_CTL_BASE_SHFT)
 
-#define DF_DRAM_BASE0		DF_REG_ID(0, 0x110)
+#define DF_DRAM_BASE0			DF_REG_ID(0, 0x110)
 #define   DRAM_BASE_REG_VALID		BIT(0)
 #define   DRAM_BASE_HOLE_EN		BIT(1)
 #define   DRAM_BASE_INTLV_CH_SHFT	4
@@ -82,4 +43,42 @@ union df_ficaa {
 #define DF_DRAM_LIMIT(dram_map_pair)	((dram_map_pair) * 2 * sizeof(uint32_t) \
 						+ DF_DRAM_LIMIT0)
 
+#define DF_MMIO_BASE0			DF_REG_ID(0, 0x200)
+#define DF_MMIO_LIMIT0			DF_REG_ID(0, 0x204)
+#define   DF_MMIO_SHIFT			16
+#define DF_MMIO_CTRL0			DF_REG_ID(0, 0x208)
+
+#define DF_MMIO_REG_SET_SIZE		4
+#define DF_MMIO_REG_SET_COUNT		8
+
+union df_mmio_control {
+	struct {
+		uint32_t re        :  1; /* [ 0.. 0] */
+		uint32_t we        :  1; /* [ 1.. 1] */
+		uint32_t           :  2; /* [ 3.. 2] */
+		uint32_t fabric_id :  8; /* [11.. 4] */
+		uint32_t np        :  1; /* [12..12] */
+		uint32_t           : 19; /* [31..13] */
+	};
+	uint32_t raw;
+};
+
+#define DF_FICAA_BIOS			DF_REG_ID(4, 0x5C)
+#define DF_FICAD_LO			DF_REG_ID(4, 0x98)
+#define DF_FICAD_HI			DF_REG_ID(4, 0x9C)
+
+union df_ficaa {
+	struct {
+		uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */
+		uint32_t                 : 1; /* [ 1.. 1] */
+		uint32_t reg_num         : 9; /* [10.. 2] */
+		uint32_t func_num        : 3; /* [13..11] */
+		uint32_t b64_en          : 1; /* [14..14] */
+		uint32_t                 : 1; /* [15..15] */
+		uint32_t inst_id         : 8; /* [23..16] */
+		uint32_t                 : 8; /* [31..24] */
+	};
+	uint32_t raw;
+};
+
 #endif /* AMD_PICASSO_DATA_FABRIC_H */