diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-16 00:30:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-17 15:45:57 +0000 |
| commit | 7a92e3895f84daab1c9051eede1d8a33446321a5 (patch) | |
| tree | 3ea9f47ce084c2c4669f3c03ef3f506e62f5fffb /src/soc/amd | |
| parent | 35f0a8fec7cd6127838fbe5a36170ba73efa49a4 (diff) | |
soc/amd/picasso/agesa_acpi: add cast before right shift
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/agesa_acpi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 758a35f043..b5982c85aa 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -554,7 +554,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 - ((dram_base_reg & DRAM_BASE_ADDR) >> DRAM_BASE_ADDR_SHFT); memory_length = memory_length << 28; - memory_base = (dram_base_reg & DRAM_BASE_ADDR) + memory_base = (uint64_t)(dram_base_reg & DRAM_BASE_ADDR) << (28 - DRAM_BASE_ADDR_SHFT); if (memory_base == 0) { @@ -572,7 +572,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, size_below_hole = hole_base - memory_base; current = create_crat_memory_entry(0, memory_base, size_below_hole, current); - memory_length = (((dram_limit_reg & DRAM_LIMIT_ADDR) + memory_length = (uint64_t)(((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 - 0x10) << 28; |