diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-11-03 23:05:03 +0100 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-11-09 15:47:31 +0000 |
| commit | 753827ef333cf1d4f08b017f197cc4337e980fd6 (patch) | |
| tree | 11a3755482a4640a1b510c0942311ea861c10d8c /src/soc/amd | |
| parent | d92bb3c3f1447e6731a9694f16338c48e5d9f954 (diff) | |
soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/acpi/soc.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index c4425ebdd8..f44f873446 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -8,6 +8,9 @@ Device(PCI0) { #include "sb_pci0_fch.asl" } +/* PCI IRQ mapping for the Southbridge */ +#include "pci_int_defs.asl" + /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> |