diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-03-23 14:53:58 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 00:00:51 +0000 |
| commit | 31f7a726ff6aba214f32c10878075ba161bbe97c (patch) | |
| tree | 6a3250ac0a7c11e5f305e44e3e3629fbde79ebeb /src/soc/amd | |
| parent | 0d2c0019e284aea3b1889579782495afb6e52daf (diff) | |
soc/amd/cezanne: save chipset state to CBMEM
Guybrush complains that this is missing during the boot, so add it to
cezanne. I verified that the registers in gpio.c are correct.
BUG=b:184549804
TEST=Build and boot
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a27b26d124..7a1146f779 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PM + select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 57c19615d9..573b353c79 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> +#include <amdblocks/pmlib.h> #include <arch/cpu.h> #include <console/console.h> #include <fsp/api.h> @@ -20,6 +21,9 @@ asmlinkage void car_stage_entry(void) post_code(0x41); + /* Snapshot chipset state prior to any FSP call */ + fill_chipset_state(); + fsp_memory_init(acpi_is_wakeup_s3()); soc_update_apob_cache(); |