soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common

The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

17 files changed, 94 insertions, 480 deletions

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index e4aa7040e6..efef2f19c9 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/data_fabric.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c
index 5dc0f99a41..6a34a07d15 100644
--- a/src/soc/amd/cezanne/data_fabric.c
+++ b/src/soc/amd/cezanne/data_fabric.c
@@ -1,102 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi_device.h>
-#include <amdblocks/data_fabric.h>
-#include <arch/hpet.h>
 #include <console/console.h>
-#include <cpu/x86/lapic_def.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/data_fabric.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-void data_fabric_set_mmio_np(void)
-{
-	/*
-	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
-	 *
-	 * AGESA has already programmed the NB MMIO routing, however nothing
-	 * is yet marked as non-posted.
-	 *
-	 * If there exists an overlapping routing base/limit pair, trim its
-	 * base or limit to avoid the new NP region.  If any pair exists
-	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
-	 * HPET-LAPIC, it must be split into two regions.
-	 *
-	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
-	 * to own everything.  If not practical, consider erasing all settings
-	 * and have coreboot reprogram them.  At that time, make the source
-	 * below more flexible.
-	 *   * Note that the code relies on the granularity of the HPET and
-	 *     LAPIC addresses being sufficiently large that the shifted limits
-	 *     +/-1 are always equivalent to the non-shifted values +/-1.
-	 */
-
-	unsigned int i;
-	int reg;
-	uint32_t base, limit, ctrl;
-	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
-
-	data_fabric_print_mmio_conf();
-
-	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
-		/* Adjust all registers that overlap */
-		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
-		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
-			continue; /* not enabled */
-
-		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
-		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
-
-		if (base > np_top || limit < np_bot)
-			continue; /* no overlap at all */
-
-		if (base >= np_bot && limit <= np_top) {
-			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
-			continue;
-		}
-
-		if (base < np_bot && limit > np_top) {
-			/* Split the configured region */
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-			reg = data_fabric_find_unused_mmio_reg();
-			if (reg < 0) {
-				/* Although a pair could be freed later, this condition is
-				 * very unusual and deserves analysis.  Flag an error and
-				 * leave the topmost part unconfigured. */
-				printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
-				continue;
-			}
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
-			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
-			continue;
-		}
-
-		/* If still here, adjust only the base or limit */
-		if (base <= np_bot)
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-		else
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
-	}
-
-	reg = data_fabric_find_unused_mmio_reg();
-	if (reg < 0) {
-		printk(BIOS_ERR, "cannot configure region as NP\n");
-		return;
-	}
-
-	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
-	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
-	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
-			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
-				   | DF_MMIO_WE | DF_MMIO_RE);
-
-	data_fabric_print_mmio_conf();
-}
 
 static const char *data_fabric_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h
index 27444befb3..1808df3044 100644
--- a/src/soc/amd/cezanne/include/soc/data_fabric.h
+++ b/src/soc/amd/cezanne/include/soc/data_fabric.h
@@ -12,6 +12,4 @@
 
 #define NUM_NB_MMIO_REGS		8
 
-void data_fabric_set_mmio_np(void);
-
 #endif /* AMD_CEZANNE_DATA_FABRIC_H */
diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
index 0fcee3642b..f1a067f4e0 100644
--- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
+++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
@@ -2,7 +2,9 @@
 
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/pci_devs.h>
+#include <arch/hpet.h>
 #include <console/console.h>
+#include <cpu/x86/lapic_def.h>
 #include <device/pci_ops.h>
 #include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
@@ -82,3 +84,89 @@ int data_fabric_find_unused_mmio_reg(void)
 	}
 	return -1;
 }
+
+void data_fabric_set_mmio_np(void)
+{
+	/*
+	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
+	 *
+	 * AGESA has already programmed the NB MMIO routing, however nothing
+	 * is yet marked as non-posted.
+	 *
+	 * If there exists an overlapping routing base/limit pair, trim its
+	 * base or limit to avoid the new NP region.  If any pair exists
+	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
+	 * HPET-LAPIC, it must be split into two regions.
+	 *
+	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
+	 * to own everything.  If not practical, consider erasing all settings
+	 * and have coreboot reprogram them.  At that time, make the source
+	 * below more flexible.
+	 *   * Note that the code relies on the granularity of the HPET and
+	 *     LAPIC addresses being sufficiently large that the shifted limits
+	 *     +/-1 are always equivalent to the non-shifted values +/-1.
+	 */
+
+	unsigned int i;
+	int reg;
+	uint32_t base, limit, ctrl;
+	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
+	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
+
+	data_fabric_print_mmio_conf();
+
+	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
+		/* Adjust all registers that overlap */
+		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
+		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
+			continue; /* not enabled */
+
+		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
+		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
+
+		if (base > np_top || limit < np_bot)
+			continue; /* no overlap at all */
+
+		if (base >= np_bot && limit <= np_top) {
+			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
+			continue;
+		}
+
+		if (base < np_bot && limit > np_top) {
+			/* Split the configured region */
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
+			reg = data_fabric_find_unused_mmio_reg();
+			if (reg < 0) {
+				/* Although a pair could be freed later, this condition is
+				 * very unusual and deserves analysis.  Flag an error and
+				 * leave the topmost part unconfigured. */
+				printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
+				continue;
+			}
+			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
+			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
+			continue;
+		}
+
+		/* If still here, adjust only the base or limit */
+		if (base <= np_bot)
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
+		else
+			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
+	}
+
+	reg = data_fabric_find_unused_mmio_reg();
+	if (reg < 0) {
+		printk(BIOS_ERR, "cannot configure region as NP\n");
+		return;
+	}
+
+	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
+	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
+	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
+			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
+				   | DF_MMIO_WE | DF_MMIO_RE);
+
+	data_fabric_print_mmio_conf();
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
index 604c24e16f..5cc7f4867b 100644
--- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h
+++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
@@ -45,5 +45,6 @@ void data_fabric_broadcast_write32(uint8_t function, uint16_t reg, uint32_t data
 void data_fabric_print_mmio_conf(void);
 void data_fabric_disable_mmio_reg(unsigned int reg);
 int data_fabric_find_unused_mmio_reg(void);
+void data_fabric_set_mmio_np(void);
 
 #endif /* AMD_BLOCK_DATA_FABRIC_H */
diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c
index b0b90ee8ad..9e9ee9eecf 100644
--- a/src/soc/amd/glinda/chip.c
+++ b/src/soc/amd/glinda/chip.c
@@ -2,13 +2,13 @@
 
 /* TODO: Update for Glinda */
 
+#include <amdblocks/data_fabric.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
diff --git a/src/soc/amd/glinda/data_fabric.c b/src/soc/amd/glinda/data_fabric.c
index 822d5a9dbf..3bc0b6d80a 100644
--- a/src/soc/amd/glinda/data_fabric.c
+++ b/src/soc/amd/glinda/data_fabric.c
@@ -3,103 +3,10 @@
 /* TODO: Update for Glinda */
 
 #include <acpi/acpi_device.h>
-#include <amdblocks/data_fabric.h>
-#include <arch/hpet.h>
 #include <console/console.h>
-#include <cpu/x86/lapic_def.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/data_fabric.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-void data_fabric_set_mmio_np(void)
-{
-	/*
-	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
-	 *
-	 * AGESA has already programmed the NB MMIO routing, however nothing
-	 * is yet marked as non-posted.
-	 *
-	 * If there exists an overlapping routing base/limit pair, trim its
-	 * base or limit to avoid the new NP region.  If any pair exists
-	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
-	 * HPET-LAPIC, it must be split into two regions.
-	 *
-	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
-	 * to own everything.  If not practical, consider erasing all settings
-	 * and have coreboot reprogram them.  At that time, make the source
-	 * below more flexible.
-	 *   * Note that the code relies on the granularity of the HPET and
-	 *     LAPIC addresses being sufficiently large that the shifted limits
-	 *     +/-1 are always equivalent to the non-shifted values +/-1.
-	 */
-
-	unsigned int i;
-	int reg;
-	uint32_t base, limit, ctrl;
-	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
-
-	data_fabric_print_mmio_conf();
-
-	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
-		/* Adjust all registers that overlap */
-		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
-		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
-			continue; /* not enabled */
-
-		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
-		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
-
-		if (base > np_top || limit < np_bot)
-			continue; /* no overlap at all */
-
-		if (base >= np_bot && limit <= np_top) {
-			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
-			continue;
-		}
-
-		if (base < np_bot && limit > np_top) {
-			/* Split the configured region */
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-			reg = data_fabric_find_unused_mmio_reg();
-			if (reg < 0) {
-				/* Although a pair could be freed later, this condition is
-				 * very unusual and deserves analysis.  Flag an error and
-				 * leave the topmost part unconfigured. */
-				printk(BIOS_ERR,
-				       "Error: Not enough NB MMIO routing registers\n");
-				continue;
-			}
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
-			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
-			continue;
-		}
-
-		/* If still here, adjust only the base or limit */
-		if (base <= np_bot)
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-		else
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
-	}
-
-	reg = data_fabric_find_unused_mmio_reg();
-	if (reg < 0) {
-		printk(BIOS_ERR, "Error: cannot configure region as NP\n");
-		return;
-	}
-
-	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
-	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
-	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
-			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
-				   | DF_MMIO_WE | DF_MMIO_RE);
-
-	data_fabric_print_mmio_conf();
-}
 
 static const char *data_fabric_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h
index 4abbb3ddd3..0bb9561064 100644
--- a/src/soc/amd/glinda/include/soc/data_fabric.h
+++ b/src/soc/amd/glinda/include/soc/data_fabric.h
@@ -14,6 +14,4 @@
 
 #define NUM_NB_MMIO_REGS		8
 
-void data_fabric_set_mmio_np(void);
-
 #endif /* AMD_GLINDA_DATA_FABRIC_H */
diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c
index 99e33ce3e7..83a485f271 100644
--- a/src/soc/amd/mendocino/chip.c
+++ b/src/soc/amd/mendocino/chip.c
@@ -2,13 +2,13 @@
 
 /* TODO: Check if this is still correct */
 
+#include <amdblocks/data_fabric.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c
index f1ee4df4b8..2569da8c67 100644
--- a/src/soc/amd/mendocino/data_fabric.c
+++ b/src/soc/amd/mendocino/data_fabric.c
@@ -1,105 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Check if this is still correct */
-
 #include <acpi/acpi_device.h>
-#include <amdblocks/data_fabric.h>
-#include <arch/hpet.h>
 #include <console/console.h>
-#include <cpu/x86/lapic_def.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/data_fabric.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-void data_fabric_set_mmio_np(void)
-{
-	/*
-	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
-	 *
-	 * AGESA has already programmed the NB MMIO routing, however nothing
-	 * is yet marked as non-posted.
-	 *
-	 * If there exists an overlapping routing base/limit pair, trim its
-	 * base or limit to avoid the new NP region.  If any pair exists
-	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
-	 * HPET-LAPIC, it must be split into two regions.
-	 *
-	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
-	 * to own everything.  If not practical, consider erasing all settings
-	 * and have coreboot reprogram them.  At that time, make the source
-	 * below more flexible.
-	 *   * Note that the code relies on the granularity of the HPET and
-	 *     LAPIC addresses being sufficiently large that the shifted limits
-	 *     +/-1 are always equivalent to the non-shifted values +/-1.
-	 */
-
-	unsigned int i;
-	int reg;
-	uint32_t base, limit, ctrl;
-	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
-
-	data_fabric_print_mmio_conf();
-
-	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
-		/* Adjust all registers that overlap */
-		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
-		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
-			continue; /* not enabled */
-
-		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
-		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
-
-		if (base > np_top || limit < np_bot)
-			continue; /* no overlap at all */
-
-		if (base >= np_bot && limit <= np_top) {
-			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
-			continue;
-		}
-
-		if (base < np_bot && limit > np_top) {
-			/* Split the configured region */
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-			reg = data_fabric_find_unused_mmio_reg();
-			if (reg < 0) {
-				/* Although a pair could be freed later, this condition is
-				 * very unusual and deserves analysis.  Flag an error and
-				 * leave the topmost part unconfigured. */
-				printk(BIOS_ERR,
-				       "Error: Not enough NB MMIO routing registers\n");
-				continue;
-			}
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
-			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
-			continue;
-		}
-
-		/* If still here, adjust only the base or limit */
-		if (base <= np_bot)
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-		else
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
-	}
-
-	reg = data_fabric_find_unused_mmio_reg();
-	if (reg < 0) {
-		printk(BIOS_ERR, "Error: cannot configure region as NP\n");
-		return;
-	}
-
-	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
-	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
-	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
-			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
-				   | DF_MMIO_WE | DF_MMIO_RE);
-
-	data_fabric_print_mmio_conf();
-}
 
 static const char *data_fabric_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h
index c7727bb484..a73bc424ef 100644
--- a/src/soc/amd/mendocino/include/soc/data_fabric.h
+++ b/src/soc/amd/mendocino/include/soc/data_fabric.h
@@ -12,6 +12,4 @@
 
 #define NUM_NB_MMIO_REGS		8
 
-void data_fabric_set_mmio_np(void);
-
 #endif /* AMD_MENDOCINO_DATA_FABRIC_H */
diff --git a/src/soc/amd/morgana/chip.c b/src/soc/amd/morgana/chip.c
index 086211e2c2..13d2638723 100644
--- a/src/soc/amd/morgana/chip.c
+++ b/src/soc/amd/morgana/chip.c
@@ -2,13 +2,13 @@
 
 /* TODO: Update for Morgana */
 
+#include <amdblocks/data_fabric.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
diff --git a/src/soc/amd/morgana/data_fabric.c b/src/soc/amd/morgana/data_fabric.c
index 2f72e3a654..6c02d21557 100644
--- a/src/soc/amd/morgana/data_fabric.c
+++ b/src/soc/amd/morgana/data_fabric.c
@@ -3,103 +3,10 @@
 /* TODO: Update for Morgana */
 
 #include <acpi/acpi_device.h>
-#include <amdblocks/data_fabric.h>
-#include <arch/hpet.h>
 #include <console/console.h>
-#include <cpu/x86/lapic_def.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/data_fabric.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-void data_fabric_set_mmio_np(void)
-{
-	/*
-	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
-	 *
-	 * AGESA has already programmed the NB MMIO routing, however nothing
-	 * is yet marked as non-posted.
-	 *
-	 * If there exists an overlapping routing base/limit pair, trim its
-	 * base or limit to avoid the new NP region.  If any pair exists
-	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
-	 * HPET-LAPIC, it must be split into two regions.
-	 *
-	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
-	 * to own everything.  If not practical, consider erasing all settings
-	 * and have coreboot reprogram them.  At that time, make the source
-	 * below more flexible.
-	 *   * Note that the code relies on the granularity of the HPET and
-	 *     LAPIC addresses being sufficiently large that the shifted limits
-	 *     +/-1 are always equivalent to the non-shifted values +/-1.
-	 */
-
-	unsigned int i;
-	int reg;
-	uint32_t base, limit, ctrl;
-	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
-
-	data_fabric_print_mmio_conf();
-
-	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
-		/* Adjust all registers that overlap */
-		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
-		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
-			continue; /* not enabled */
-
-		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
-		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
-
-		if (base > np_top || limit < np_bot)
-			continue; /* no overlap at all */
-
-		if (base >= np_bot && limit <= np_top) {
-			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
-			continue;
-		}
-
-		if (base < np_bot && limit > np_top) {
-			/* Split the configured region */
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-			reg = data_fabric_find_unused_mmio_reg();
-			if (reg < 0) {
-				/* Although a pair could be freed later, this condition is
-				 * very unusual and deserves analysis.  Flag an error and
-				 * leave the topmost part unconfigured. */
-				printk(BIOS_ERR,
-				       "Error: Not enough NB MMIO routing registers\n");
-				continue;
-			}
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
-			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
-			continue;
-		}
-
-		/* If still here, adjust only the base or limit */
-		if (base <= np_bot)
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-		else
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
-	}
-
-	reg = data_fabric_find_unused_mmio_reg();
-	if (reg < 0) {
-		printk(BIOS_ERR, "Error: cannot configure region as NP\n");
-		return;
-	}
-
-	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
-	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
-	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
-			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
-				   | DF_MMIO_WE | DF_MMIO_RE);
-
-	data_fabric_print_mmio_conf();
-}
 
 static const char *data_fabric_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/amd/morgana/include/soc/data_fabric.h b/src/soc/amd/morgana/include/soc/data_fabric.h
index eba4cd8b98..c210e473e1 100644
--- a/src/soc/amd/morgana/include/soc/data_fabric.h
+++ b/src/soc/amd/morgana/include/soc/data_fabric.h
@@ -14,6 +14,4 @@
 
 #define NUM_NB_MMIO_REGS		8
 
-void data_fabric_set_mmio_np(void);
-
 #endif /* AMD_MORGANA_DATA_FABRIC_H */
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 37e62e2b8f..fc30af9dda 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/data_fabric.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/data_fabric.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c
index ddc280bc67..a25115886e 100644
--- a/src/soc/amd/picasso/data_fabric.c
+++ b/src/soc/amd/picasso/data_fabric.c
@@ -1,102 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi_device.h>
-#include <amdblocks/data_fabric.h>
-#include <arch/hpet.h>
 #include <console/console.h>
-#include <cpu/x86/lapic_def.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <soc/data_fabric.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-void data_fabric_set_mmio_np(void)
-{
-	/*
-	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
-	 *
-	 * AGESA has already programmed the NB MMIO routing, however nothing
-	 * is yet marked as non-posted.
-	 *
-	 * If there exists an overlapping routing base/limit pair, trim its
-	 * base or limit to avoid the new NP region.  If any pair exists
-	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
-	 * HPET-LAPIC, it must be split into two regions.
-	 *
-	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
-	 * to own everything.  If not practical, consider erasing all settings
-	 * and have coreboot reprogram them.  At that time, make the source
-	 * below more flexible.
-	 *   * Note that the code relies on the granularity of the HPET and
-	 *     LAPIC addresses being sufficiently large that the shifted limits
-	 *     +/-1 are always equivalent to the non-shifted values +/-1.
-	 */
-
-	unsigned int i;
-	int reg;
-	uint32_t base, limit, ctrl;
-	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
-
-	data_fabric_print_mmio_conf();
-
-	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
-		/* Adjust all registers that overlap */
-		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
-		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
-			continue; /* not enabled */
-
-		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
-		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
-
-		if (base > np_top || limit < np_bot)
-			continue; /* no overlap at all */
-
-		if (base >= np_bot && limit <= np_top) {
-			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
-			continue;
-		}
-
-		if (base < np_bot && limit > np_top) {
-			/* Split the configured region */
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-			reg = data_fabric_find_unused_mmio_reg();
-			if (reg < 0) {
-				/* Although a pair could be freed later, this condition is
-				 * very unusual and deserves analysis.  Flag an error and
-				 * leave the topmost part unconfigured. */
-				printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
-				continue;
-			}
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
-			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
-			continue;
-		}
-
-		/* If still here, adjust only the base or limit */
-		if (base <= np_bot)
-			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
-		else
-			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
-	}
-
-	reg = data_fabric_find_unused_mmio_reg();
-	if (reg < 0) {
-		printk(BIOS_ERR, "cannot configure region as NP\n");
-		return;
-	}
-
-	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
-	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
-	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
-			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
-				   | DF_MMIO_WE | DF_MMIO_RE);
-
-	data_fabric_print_mmio_conf();
-}
 
 static const char *data_fabric_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h
index 5533433126..054ca89e48 100644
--- a/src/soc/amd/picasso/include/soc/data_fabric.h
+++ b/src/soc/amd/picasso/include/soc/data_fabric.h
@@ -49,6 +49,4 @@
 #define DF_DRAM_LIMIT(dram_map_pair)	((dram_map_pair) * 2 * sizeof(uint32_t) \
 						+ D18F0_DRAM_LIMIT0)
 
-void data_fabric_set_mmio_np(void);
-
 #endif /* AMD_PICASSO_DATA_FABRIC_H */