soc/amd/cezanne/mca: add and use mca_bank_name[]

This enables the MCAX checking and BERT entry generation for Cezanne.

TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706

Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 38 insertions, 3 deletions

diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c
index 77006a713c..778b8e7b57 100644
--- a/src/soc/amd/cezanne/mca.c
+++ b/src/soc/amd/cezanne/mca.c
@@ -1,19 +1,54 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/mca.h>
+#include <cpu/x86/msr.h>
 #include <types.h>
 
+static const char *const mca_bank_name[] = {
+	[0]  = "Load-store unit",
+	[1]  = "Instruction fetch unit",
+	[2]  = "L2 cache unit",
+	[3]  = "Decode unit",
+	[4]  = "",
+	[5]  = "Execution unit",
+	[6]  = "Floating point unit",
+	[7]  = "L3 cache unit",
+	[8]  = "L3 cache unit",
+	[9]  = "L3 cache unit",
+	[10] = "L3 cache unit",
+	[11] = "L3 cache unit",
+	[12] = "L3 cache unit",
+	[13] = "L3 cache unit",
+	[14] = "L3 cache unit",
+	[15] = "",
+	[16] = "",
+	[17] = "UMC",
+	[18] = "UMC",
+	[19] = "CS",
+	[20] = "CS",
+	[21] = "",
+	[22] = "",
+	[23] = "",
+	[24] = "",
+	[25] = "",
+	[26] = "",
+	[27] = "PIE",
+};
+
 bool mca_has_expected_bank_count(void)
 {
-	return true;
+	return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count();
 }
 
 bool mca_is_valid_bank(unsigned int bank)
 {
-	return false;
+	return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL);
 }
 
 const char *mca_get_bank_name(unsigned int bank)
 {
-	return "";
+	if (mca_is_valid_bank(bank))
+		return mca_bank_name[bank];
+	else
+		return "";
 }