diff options
| author | Ivy Jian <ivy.jian@quanta.corp-partner.google.com> | 2023-05-11 10:37:10 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-06-20 10:38:19 +0000 |
| commit | 2eaa25a9d376ea7ebfc5befda8729956645e7b16 (patch) | |
| tree | 52d5c35d77509520cb0396b30bbebc13f027a01d /src/soc/amd | |
| parent | 1e13a2cfd6be4152dc5011be42dce71a819cb546 (diff) | |
mb/google/rex/var/rex0: Configure I2C timing for I2C devices
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices
meet timing requirement. Note that I2C5 timing will be updated
separately when the tuning done
BUG=b:280559903
TEST=Build and check I2C devices timing meet spec.
| | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 |
|-------------|------------|----------|--------|-------|---------|
| FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 |
| TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 |
| THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 |
| THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 |
| TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 |
| TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 |
| TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 |
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions