diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-07-29 00:44:25 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-30 15:58:28 +0000 |
| commit | 27c9762f95da4c16721245daf60f924aa066adae (patch) | |
| tree | d162f71b1fafb3ca230a6f2043e16bd8bd66cea0 /src/soc/amd | |
| parent | 23ade0ee150fd7e3dcd44d5ab265bc2403b321c2 (diff) | |
soc/amd/picasso: Split ops for internal and external PCIe GPP bridges
This change splits the device operations for internal and external PCIe
GPP bridges so that the external bridges use `pciexp_scan_bridge()`
instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for
external GPP bridges to enable ASPM on downstream devices if supported.
BUG=b:162352484
TEST=Verified on Trembyle:
$ lspci -s 1:00.0 -vvv | grep ASPM
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/pcie_gpp.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 73de80365d..96d33f2f1f 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <device/pciexp.h> #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <stdio.h> @@ -36,7 +37,7 @@ static const char *pcie_gpp_acpi_name(const struct device *dev) return NULL; } -static struct device_operations pcie_gpp_ops = { +static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -47,14 +48,29 @@ static struct device_operations pcie_gpp_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA, PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB, 0 }; -static const struct pci_driver pcie_gpp_driver __pci_driver = { - .ops = &pcie_gpp_ops, +static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { + .ops = &internal_pcie_gpp_ops, .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; + +static struct device_operations external_pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const struct pci_driver external_pcie_gpp_driver __pci_driver = { + .ops = &external_pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, +}; |