diff options
| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2018-08-16 22:49:49 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-17 21:10:34 +0000 |
| commit | 108bf2951648a6953fa96d79fd591868c43da147 (patch) | |
| tree | cd66ca0a1b692808c84c2ed7cc164cb0dc18fd43 /src/soc/amd | |
| parent | 24462e65076372dd15cc6587a04fc2c49a9afe5a (diff) | |
google/grunt: Update TP/TS/H1 i2c timings
After adjustment on Careena EVT
TP: 400.0 KHz
TS: 396.8 KHz
H1: 396.8 KHz
BUG=b:112663934,b:112664258
BRANCH=master
TEST=emerge-grunt coreboot
measure by scope
Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28119
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions