diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-29 22:31:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-31 01:09:18 +0000 |
| commit | ee04881360db7d551cfa49ca80b9b1c21a466439 (patch) | |
| tree | 7347629609311df4724dbb81cfa6389ed93f9994 /src/soc/amd | |
| parent | 5ddcfe5ec17b4b625e7969157a819e931a68d330 (diff) | |
soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/psp.c | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/psp.c | 4 |
4 files changed, 6 insertions, 7 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 8cd8236706..9d56d6beee 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -3,6 +3,8 @@ #ifndef AMD_BLOCK_PSP_H #define AMD_BLOCK_PSP_H +#define MSR_PSP_ADDR 0xc00110a2 + /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void); diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index 6a4a1ea821..ddefd22bd0 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -8,15 +8,14 @@ #include <amdblocks/smi.h> #define PSP_MAILBOX_OFFSET 0x10570 -#define MSR_CU_CBBCFG 0xc00110a2 void *soc_get_mbox_address(void) { uintptr_t psp_mmio; - psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + psp_mmio = rdmsr(MSR_PSP_ADDR).lo; if (psp_mmio == 0xffffffff) { - printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n"); + printk(BIOS_WARNING, "PSP: MSR_PSP_ADDR uninitialized\n"); return 0; } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 8d8203516c..219af8437a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -205,8 +205,6 @@ void soc_enable_psp_early(void); #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ #define PSP_MAILBOX_BAR_EN BIT(4) -#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index c24b8be1df..a7fead73dc 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -44,9 +44,9 @@ void *soc_get_mbox_address(void) /* Determine if Bar3Hide has been set, and if hidden get the base from * the MSR instead. */ if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(MSR_CU_CBBCFG).lo; + psp_mmio = rdmsr(MSR_PSP_ADDR).lo; if (psp_mmio == 0xffffffff) { - printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n"); + printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n"); return 0; } } else { |