diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-06 10:46:36 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-13 19:01:36 +0000 |
| commit | e2697de821ed1f97199ce3bc08cb85b396c96715 (patch) | |
| tree | 828daf53f0fcd01e35890d1487383d0bdcf86517 /src/soc/amd | |
| parent | b00ba2ae6bd9da0f03dfecd63504e92e1e221095 (diff) | |
amd/stoneyridge: Simplify SB link routing
Remove the check for the southbridge link from Stoney Ridge. The APU
is an SoC which can never be installed in a multi-node system. It is
pointless to detect and remember the sblink value, which is set by
hardware and comes up 0. The BKDG marks this as a reserved field vs.
documentation for multi-node-capable Family 15h devices.
Because there is only one option for SB link now, relocate the register
write done by set_vga_enable_reg() and remove the function.
Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index eacd82eccf..8e3c13c485 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -58,7 +58,6 @@ typedef struct dram_base_mask { } dram_base_mask_t; static unsigned int node_nums; -static unsigned int sblink; static device_t __f0_dev; static device_t __f1_dev; static device_t __f2_dev; @@ -143,18 +142,6 @@ static void f1_write_config32(unsigned int reg, u32 value) pci_write_config32(__f1_dev, reg, value); } -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid << 4) | (linkn << 12); - /* Routes: - * mmio 0xa0000:0xbffff - * io 0x3b0:0x3bb, 0x3c0:0x3df - */ - f1_write_config32(0xf4, val); -} - static void read_resources(device_t dev) { /* @@ -228,9 +215,8 @@ static void create_vga_resource(device_t dev) if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s link %d has VGA device\n", - dev_path(dev), sblink); - set_vga_enable_reg(0, sblink); + printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); + f1_write_config32(0xf4, 1); /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ } static void set_resources(device_t dev) @@ -605,8 +591,6 @@ void domain_set_resources(device_t dev) /* first node */ static void sysconf_init(device_t dev) { - /* don't forget sublink1 */ - sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; /* NodeCnt[2:0] */ node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; } |