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authorJulius Werner <jwerner@chromium.org>2017-11-03 15:23:09 -0700
committerJulius Werner <jwerner@chromium.org>2017-11-06 20:47:50 +0000
commit1ab8c01050c539b1af9edc5d2fd13a79bb71d053 (patch)
treeaf4e6ecd1cd46348abf8ae08ffcce7de6a2a881d /src/soc/amd
parent59e9080dcb136e2f4227a65140010aa442206dda (diff)
gru: Fix and export SPK_PA_EN GPIO for Scarlet
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On Scarlet, we instead moved the audio codec enable (previously on GPIO1_A2) there. Unfortunately the code still had some hardcoded leftovers that were overlooked in the initial port and make our speakers smell weird. This patch fixes the incorrect GPIO settings and adds the speaker enable pin to the GPIOs passed through the coreboot table, so that depthcharge doesn't have to keep its own definition of the pin which may go out of sync. Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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