diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-20 10:24:28 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-27 16:27:17 +0000 |
| commit | 9db8a44081543088caa3f396b570c538064f2fe6 (patch) | |
| tree | 3361356593ba7b657bdcd5beae667d2c5daaa3d9 /src/soc/amd | |
| parent | 6c747068565f32b282f13cdd3aabe6afb4c66799 (diff) | |
amd/stoneyridge: Move AmdInitEnv to ramstage
Relocate the call to AGESA in preparation for implementing postcar.
This change should have no net effect as long as the ordering is
maintained and AmdInitEnv stays later than CAR teardown.
BUG=b:66196801
Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 12 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 6 |
2 files changed, 13 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 325d2ea82e..c230fe7017 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -14,6 +14,8 @@ */ #include <chip.h> +#include <bootstate.h> +#include <console/console.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <device/device.h> @@ -21,6 +23,8 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> +#include <agesawrapper.h> +#include <agesawrapper_call.h> struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, @@ -75,3 +79,11 @@ struct chip_operations soc_amd_stoneyridge_ops = { .init = &soc_init, .final = &soc_final }; + +static void do_initenv(void *unused) +{ + post_code(0x46); + AGESAWRAPPER(amdinitenv); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, do_initenv, NULL); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index b062c6c4a9..6769a262f0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -72,14 +72,10 @@ asmlinkage void car_stage_entry(void) /* * This writes contents to DRAM backing before teardown. - * todo: move CAR teardown to postcar implementation and - * relocate amdinitenv to ramstage. + * todo: move CAR teardown to postcar implementation. */ chipset_teardown_car(); - post_code(0x44); - AGESAWRAPPER(amdinitenv); - post_code(0x50); run_ramstage(); |