diff options
author | Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> | 2020-01-19 16:32:08 -0700 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2020-04-02 16:04:22 +0000 |
commit | 737e56aa56e5dce6c682580f8e89b80a0119107f (patch) | |
tree | 75f38d89e6225c4094a48dcfc3ce3a8fd5d3a66f /src/soc/amd | |
parent | 5646a648dfc7fcc53ff4dc86ddbc40620ee4a86c (diff) |
soc/amd/common/psp: Consolidate FW blob load functions
The commands used in Family 15h for loading the SMU FW blobs out of
flash had already been defined differently in Family 17h. To begin
removing Family 15h dependencies from the common/psp, change the
definitions of blob type to no longer match the Family 15h commands.
Consolidate the two functions used for interpreting the command and
applying the command into a single one.
BUG=b:130660285
TEST: Verify PSP functionality on google/grunt
Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/2020364
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Tested-by: Eric Peers <epeers@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp.h | 7 | ||||
-rw-r--r-- | src/soc/amd/common/block/psp/psp.c | 63 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 2 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 2 |
4 files changed, 39 insertions, 35 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index b730293bb5..494f1744f0 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -115,6 +115,11 @@ int psp_notify_dram(void); * MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob. * name: cbfs file name */ -int psp_load_named_blob(int type, const char *name); +enum psp_blob_type { + BLOB_SMU_FW, + BLOB_SMU_FW2, +}; + +int psp_load_named_blob(enum psp_blob_type type, const char *name); #endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 0294422c3d..9c053c2c39 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -288,53 +288,52 @@ static void psp_notify_boot_done(void *unused) /* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ -static int psp_load_blob(int type, void *addr) +int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; + u32 command; + void *blob; + struct cbfsf cbfs_file; + struct region_device rdev; - if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { - printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); - return PSPSTS_UNSUPPORTED; - } - - /* only two types currently supported */ - if (type != MBOX_BIOS_CMD_SMU_FW && type != MBOX_BIOS_CMD_SMU_FW2) { + switch (type) { + case BLOB_SMU_FW: + command = MBOX_BIOS_CMD_SMU_FW; + break; + case BLOB_SMU_FW2: + command = MBOX_BIOS_CMD_SMU_FW2; + break; + default: printk(BIOS_ERR, "BUG: Invalid PSP blob type %x\n", type); - return PSPSTS_INVALID_BLOB; + return -PSPSTS_INVALID_BLOB; } - printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, addr); - - /* Blob commands use the buffer registers as data, not pointer to buf */ - cmd_status = send_psp_command(type, addr); - - print_cmd_status(cmd_status, NULL); - - return cmd_status; -} - -int psp_load_named_blob(int type, const char *name) -{ - void *blob; - struct cbfsf cbfs_file; - struct region_device rdev; - int r; + /* type can only be BLOB_SMU_FW or BLOB_SMU_FW2 here, so don't re-check for this */ + if (!CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) { + printk(BIOS_ERR, "BUG: Selectable firmware is not supported\n"); + return -PSPSTS_UNSUPPORTED; + } if (cbfs_boot_locate(&cbfs_file, name, NULL)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); - if (blob) { - r = psp_load_blob(type, blob); - rdev_munmap(&rdev, blob); - } else { + if (!blob) { printk(BIOS_ERR, "BUG: Cannot map blob for PSP loading\n"); - return PSPSTS_INVALID_NAME; + return -PSPSTS_INVALID_NAME; } - return r; + + printk(BIOS_DEBUG, "PSP: Load blob type %x from @%p... ", type, blob); + + /* Blob commands use the buffer registers as data, not pointer to buf */ + cmd_status = send_psp_command(command, blob); + print_cmd_status(cmd_status, NULL); + + rdev_munmap(&rdev, blob); + return cmd_status; } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index aa3c322813..f08c12f32f 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -160,7 +160,7 @@ static void earliest_ramstage(void *unused) if (!s3_resume) { post_code(0x46); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0a209b0260..efe75b72e3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -61,7 +61,7 @@ static void load_smu_fw1(void) cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); + psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); } static void agesa_call(void) |