diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 21:42:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:25:27 +0000 |
| commit | e4500c653057759e219418a104c2f2224480e0de (patch) | |
| tree | 3dc77390435a62e1a5fbb504e63a3508d490d51c /src/soc/amd | |
| parent | 8cab80c84f2be22e1f45a2b31c8019695b70abb2 (diff) | |
soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro
When instantiated in the DSDT, this macro will expand to the static part
of the PCIe root bridge device. This macro allows both to deduplicate
parts of the DSDT code as well as adding more than one PCIe root bridge
device in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75568
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/acpi/pci_root.asl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/common/acpi/pci_root.asl b/src/soc/amd/common/acpi/pci_root.asl new file mode 100644 index 0000000000..46d15b7b8d --- /dev/null +++ b/src/soc/amd/common/acpi/pci_root.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ROOT_BRIDGE(acpi_name) \ + Device(acpi_name) { \ + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ \ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ \ + Method (_OSC, 4, NotSerialized) { \ + /* Check for proper PCI/PCIe UUID */ \ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) \ + { \ + /* Let OS control everything */ \ + Return(Arg3) \ + } Else { \ + CreateDWordField(Arg3, 0, CDW1) \ + CDW1 = CDW1 | 4 /* Unrecognized UUID, so set bit 2 to 1 */ \ + Return(Arg3) \ + } \ + } \ + } |