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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-07-22 19:16:03 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-30 17:32:49 +0000 |
| commit | c72df501a1f04df8ea6b03b97b7ddd0882c9ba19 (patch) | |
| tree | a0193ca37b154d899e98aba73dc09fdaa79cfd0c /src/soc/amd | |
| parent | 5f524809e97dd634920a434680e5d0ffa0929608 (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01
The headers added are generated as per FSP v2265_01.
Previous FSP version was v2237_00.
Changes Include:
- Add Irms UPD in FspsUpd.h
- Adjust Reserved UPD Offset in FspsUpd.h
- Few UPDs description update in FspmUpd.h
BUG=b:194032028
BRANCH=None
TEST=Build and boot brya
Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f
Cq-Depend:chrome-internal:4004482
Cq-Depend:chrome-internal:4003608
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions