arch/x86: Add a common romstage entry

It might be possible to have this used for more than x86, but that
will be for a later commit.

Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>

4 files changed, 22 insertions, 38 deletions

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 96285710e3..7a395bdf9b 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -8,18 +8,12 @@
 #include <console/console.h>
 #include <fsp/api.h>
 #include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
 
-asmlinkage void car_stage_entry(void)
+void __noreturn romstage_main(void)
 {
-	timestamp_add_now(TS_ROMSTAGE_START);
-
 	post_code(0x40);
 
-	console_init();
-
-	post_code(0x41);
-
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
 
@@ -31,4 +25,5 @@ asmlinkage void car_stage_entry(void)
 	memmap_stash_early_dram_usage();
 
 	run_ramstage();
+	die("failed to load ramstage\n");
 }
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 359eacf4b7..e66f423d52 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -8,19 +8,13 @@
 #include <console/console.h>
 #include <fsp/api.h>
 #include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
 #include <types.h>
 
-asmlinkage void car_stage_entry(void)
+void __noreturn romstage_main(void)
 {
-	timestamp_add_now(TS_ROMSTAGE_START);
-
 	post_code(0x40);
 
-	console_init();
-
-	post_code(0x42);
-
 	/* Snapshot chipset state prior to any FSP call. */
 	fill_chipset_state();
 
@@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void)
 	run_ramstage();
 
 	post_code(0x50); /* Should never see this post code. */
+	die("failed to load ramstage\n");
 }
diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c
index 49ca223c60..c5dfbdaa18 100644
--- a/src/soc/amd/sabrina/romstage.c
+++ b/src/soc/amd/sabrina/romstage.c
@@ -10,18 +10,12 @@
 #include <console/console.h>
 #include <fsp/api.h>
 #include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
 
-asmlinkage void car_stage_entry(void)
+void __noreturn romstage_main(void)
 {
-	timestamp_add_now(TS_ROMSTAGE_START);
-
 	post_code(0x40);
 
-	console_init();
-
-	post_code(0x41);
-
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
 
@@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void)
 	memmap_stash_early_dram_usage();
 
 	run_ramstage();
+	die("failed to load ramstage\n");
 }
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index be40e2171c..973e6090c5 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -1,28 +1,29 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/agesawrapper_call.h>
 #include <amdblocks/biosram.h>
-#include <device/pci_ops.h>
+#include <amdblocks/psp.h>
 #include <arch/cpu.h>
 #include <arch/romstage.h>
-#include <acpi/acpi.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
+#include <elog.h>
 #include <program_loading.h>
+#include <romstage_common.h>
 #include <romstage_handoff.h>
-#include <elog.h>
-#include <amdblocks/agesawrapper.h>
-#include <amdblocks/agesawrapper_call.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
-#include <amdblocks/psp.h>
 #include <stdint.h>
 
 #include "chip.h"
@@ -47,8 +48,7 @@ static void bsp_agesa_call(void)
 	set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
 	agesa_call();
 }
-
-asmlinkage void car_stage_entry(void)
+void __noreturn romstage_main(void)
 {
 	msr_t base, mask;
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
@@ -56,8 +56,6 @@ asmlinkage void car_stage_entry(void)
 	int s3_resume = acpi_is_wakeup_s3();
 	int i;
 
-	console_init();
-
 	soc_enable_psp_early();
 	if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 		psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
@@ -121,6 +119,7 @@ asmlinkage void car_stage_entry(void)
 
 	post_code(0x44);
 	prepare_and_run_postcar();
+	die("failed to load postcar\n");
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)