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authorJakub Czapiga <jacz@semihalf.com>2022-02-15 11:50:31 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-08 16:06:33 +0000
commitad6157ebdfddc39b95e388487e00cadd2bbf368b (patch)
treebbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/soc/amd
parente96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff)
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/romstage.c2
-rw-r--r--src/soc/amd/common/block/apob/apob_cache.c4
-rw-r--r--src/soc/amd/common/pi/agesawrapper.c20
-rw-r--r--src/soc/amd/picasso/romstage.c2
-rw-r--r--src/soc/amd/sabrina/romstage.c2
5 files changed, 15 insertions, 15 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 9e863c3966..96285710e3 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -12,7 +12,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index b932458ec2..f20337734d 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -171,7 +171,7 @@ static void soc_update_apob_cache(void *unused)
printk(BIOS_DEBUG, "APOB valid copy is already in flash\n");
if (!update_needed) {
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
return;
}
@@ -199,7 +199,7 @@ static void soc_update_apob_cache(void *unused)
return;
}
- timestamp_add_now(TS_AMD_APOB_DONE);
+ timestamp_add_now(TS_AMD_APOB_END);
printk(BIOS_INFO, "Updated APOB in flash\n");
}
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c
index 8ee962b7b0..c5e6cac465 100644
--- a/src/soc/amd/common/pi/agesawrapper.c
+++ b/src/soc/amd/common/pi/agesawrapper.c
@@ -102,7 +102,7 @@ static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams)
timestamp_add_now(TS_AGESA_INIT_RESET_START);
status = amd_dispatch(ResetParams);
- timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESET_END);
return status;
}
@@ -116,7 +116,7 @@ static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams)
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
status = amd_dispatch(EarlyParams);
- timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);
+ timestamp_add_now(TS_AGESA_INIT_EARLY_END);
return status;
}
@@ -173,7 +173,7 @@ static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams)
timestamp_add_now(TS_AGESA_INIT_POST_START);
status = amd_dispatch(PostParams);
- timestamp_add_now(TS_AGESA_INIT_POST_DONE);
+ timestamp_add_now(TS_AGESA_INIT_POST_END);
/*
* AGESA passes back the base and size of UMA. This is the only
@@ -208,7 +208,7 @@ static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams)
timestamp_add_now(TS_AGESA_INIT_ENV_START);
status = amd_dispatch(EnvParams);
- timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
+ timestamp_add_now(TS_AGESA_INIT_ENV_END);
return status;
}
@@ -251,7 +251,7 @@ static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams)
timestamp_add_now(TS_AGESA_INIT_MID_START);
status = amd_dispatch(MidParams);
- timestamp_add_now(TS_AGESA_INIT_MID_DONE);
+ timestamp_add_now(TS_AGESA_INIT_MID_END);
return status;
}
@@ -268,7 +268,7 @@ static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams)
timestamp_add_now(TS_AGESA_INIT_LATE_START);
Status = amd_dispatch(LateParams);
- timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
+ timestamp_add_now(TS_AGESA_INIT_LATE_END);
DmiTable = LateParams->DmiTable;
AcpiPstate = LateParams->AcpiPState;
@@ -295,7 +295,7 @@ static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams)
timestamp_add_now(TS_AGESA_INIT_RTB_START);
Status = amd_dispatch(RtbParams);
- timestamp_add_now(TS_AGESA_INIT_RTB_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RTB_END);
if (Status != AGESA_SUCCESS)
return Status;
@@ -314,7 +314,7 @@ static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams)
timestamp_add_now(TS_AGESA_INIT_RESUME_START);
status = amd_dispatch(InitResumeParams);
- timestamp_add_now(TS_AGESA_INIT_RESUME_DONE);
+ timestamp_add_now(TS_AGESA_INIT_RESUME_END);
return status;
}
@@ -329,7 +329,7 @@ static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams)
timestamp_add_now(TS_AGESA_S3_LATE_START);
Status = amd_dispatch(S3LateParams);
- timestamp_add_now(TS_AGESA_S3_LATE_DONE);
+ timestamp_add_now(TS_AGESA_S3_LATE_END);
return Status;
}
@@ -342,7 +342,7 @@ static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams)
timestamp_add_now(TS_AGESA_S3_FINAL_START);
Status = amd_dispatch(S3FinalParams);
- timestamp_add_now(TS_AGESA_S3_FINAL_DONE);
+ timestamp_add_now(TS_AGESA_S3_FINAL_END);
return Status;
}
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 197241084f..359eacf4b7 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -13,7 +13,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);
diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c
index 91f80ef4fd..49ca223c60 100644
--- a/src/soc/amd/sabrina/romstage.c
+++ b/src/soc/amd/sabrina/romstage.c
@@ -14,7 +14,7 @@
asmlinkage void car_stage_entry(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
post_code(0x40);