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authorFelix Held <felix-coreboot@felixheld.de>2022-02-07 17:22:57 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-10 17:06:14 +0000
commit736d68c0b36e8e56aa047b8c8556fb4bd196cd62 (patch)
tree0cf8666a94fad8c8ed26749d022faaab80ea7285 /src/soc/amd
parentceccfa22ba2c794d3f20b4fd22be969b8ffaea0d (diff)
soc/amd/sabrina/mca: update MCA bank names to match the hardware
The MCA bank names were checked against PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b947e686a0306d4468203103f91107c15ececc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/sabrina/mca.c23
1 files changed, 6 insertions, 17 deletions
diff --git a/src/soc/amd/sabrina/mca.c b/src/soc/amd/sabrina/mca.c
index b2f5e96f8b..511a1a805a 100644
--- a/src/soc/amd/sabrina/mca.c
+++ b/src/soc/amd/sabrina/mca.c
@@ -18,23 +18,12 @@ static const char *const mca_bank_name[] = {
[8] = "L3 cache unit",
[9] = "L3 cache unit",
[10] = "L3 cache unit",
- [11] = "L3 cache unit",
- [12] = "L3 cache unit",
- [13] = "L3 cache unit",
- [14] = "L3 cache unit",
- [15] = "",
- [16] = "",
- [17] = "UMC",
- [18] = "UMC",
- [19] = "CS",
- [20] = "CS",
- [21] = "",
- [22] = "",
- [23] = "",
- [24] = "",
- [25] = "",
- [26] = "",
- [27] = "PIE",
+ [11] = "UMC",
+ [12] = "UMC",
+ [13] = "CS",
+ [14] = "CS",
+ [15] = "NBIO",
+ [16] = "PIE",
};
bool mca_has_expected_bank_count(void)