diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-14 20:08:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-11 11:04:36 +0000 |
| commit | 663c57731185dcd25436f9ba8ebf4550d6ad4ae7 (patch) | |
| tree | db963c40a19274ef763c31a61012e0f87f091813 /src/soc/amd | |
| parent | 543c1ee31497f97337e6e955334fc08da673b6e8 (diff) | |
soc/amd/genoa: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.
Add USB OC pins to chipset.cb
In the process of scrubbing opensil for public release USB became non
functional.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/genoa/chip.h | 54 | ||||
| -rw-r--r-- | src/soc/amd/genoa/chipset.cb | 6 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/soc_chip.h | 8 |
3 files changed, 68 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h index bca40af070..d7da0bb41e 100644 --- a/src/soc/amd/genoa/chip.h +++ b/src/soc/amd/genoa/chip.h @@ -9,11 +9,65 @@ #include <soc/iomap.h> #include <types.h> +struct usb31_phy_settings { + uint8_t rx_ana_iq_phase_adjust; + uint8_t rx_eq_delta_iq_ovrd_en; + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_iq_phase_adjust; + uint8_t tx_vboost_lvl_en; + uint8_t tx_vboost_lvl; + uint8_t rx_vref_ctrl_en; + uint8_t rx_vref_ctrl; + uint8_t tx_vboost_lvl_en_x; + uint8_t tx_vboost_lvl_x; + uint8_t rx_vref_ctrl_en_x; + uint8_t rx_vref_ctrl_x; +}; + +struct soc_usb_config { + uint8_t xhci0_enable : 1; + uint8_t xhci1_enable : 1; + uint8_t xhci2_enable : 1; + struct { + uint8_t port0 : 4; + uint8_t port1 : 4; + uint8_t port2 : 4; + uint8_t port3 : 4; + uint8_t port4 : 4; + uint8_t port5 : 4; + uint8_t port6 : 4; + uint8_t port7 : 4; + } usb2_oc_pins[2]; + struct { + uint8_t port0 : 4; + uint8_t port1 : 4; + uint8_t port2 : 4; + uint8_t port3 : 4; + } usb3_oc_pins[2]; + bool polarity_cfg_low; + union { + struct { + uint8_t port0 : 2; + uint8_t port1 : 2; + uint8_t port2 : 2; /* Broken in OpenSIL */ + uint8_t port3 : 2; /* Broken in OpenSIL */ + }; + uint8_t raw; + } usb3_force_gen1; + bool usb31_phy_enable; + struct usb31_phy_settings usb31_phy[8]; + bool s1_usb31_phy_enable; + struct usb31_phy_settings s1_usb31_phy[8]; + +}; + struct soc_amd_genoa_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + + struct soc_usb_config usb; }; #endif diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 60918e9bf1..83a708255d 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -3,6 +3,12 @@ chip soc/amd/genoa device cpu_cluster 0 on ops amd_cpu_bus_ops end + # OC pins + register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }" + register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }" + device domain 0 on ops genoa_pci_domain_ops device pci 00.0 alias gnb_0 on end diff --git a/src/soc/amd/genoa/include/soc/soc_chip.h b/src/soc/amd/genoa/include/soc/soc_chip.h new file mode 100644 index 0000000000..d5dae9add8 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GENOA_SOC_CHIP_H_ +#define _SOC_GENOA_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif |