diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-06-25 11:24:38 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-07-18 15:17:30 +0000 |
| commit | 61f44127f0c06688343fdfa3f518a58b4efe170c (patch) | |
| tree | 869a1413ce1c155ef489dfe6a6bd643b777f75b7 /src/soc/amd | |
| parent | fca58334c8e08427ff9f87e5d121f487d7f45484 (diff) | |
soc/amd/cezanne: Start loading APOB asynchronously
This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This
will allow the APOB to start loading while FSP-S executes.
BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.
Starting APOB preload
APOB thread running
spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536
took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536
<ramstage doing work>
spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0
<more work..>
waiting for thread
took 0 us
APOB valid copy is already in flash
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_s_params.c | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 71cca6a11b..5da70f4e0b 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -18,6 +18,7 @@ config SOC_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE + select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -69,6 +70,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SSE2 + select TIMER_QUEUE select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index ae51f9254a..96dc61bf80 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <fsp/api.h> +#include <amdblocks/apob_cache.h> #include <device/pci.h> +#include <fsp/api.h> static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { @@ -13,4 +14,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *scfg = &supd->FspsConfig; fsp_assign_vbios_upds(scfg); + + /* + * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB + * before FSP-S was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs + * no SPI operations, we can read the APOB while FSP-S executes. + */ + start_apob_cache_read(); } |