diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-03-25 11:22:47 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-07 22:48:43 +0000 |
| commit | 5f5ca0c6f1b552d9f1bea58ff300926843d39547 (patch) | |
| tree | 46024d38c007e215cb7a46b771292fb5320fcecb /src/soc/amd | |
| parent | ac57311575e3ca08504d5640c437e96aa8c12333 (diff) | |
vc/amd/fsp/cezanne: update UPD headers
The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_s_params.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index cb60c89816..083a82d90c 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -16,7 +16,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); - mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; mcfg->serial_port_baudrate = get_uart_baudrate(); mcfg->serial_port_refclk = uart_platform_refclk(); } diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index b117afb75c..ae51f9254a 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -5,7 +5,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { - scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |