diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-07 23:16:47 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-11 11:02:31 +0000 |
| commit | 543c1ee31497f97337e6e955334fc08da673b6e8 (patch) | |
| tree | a90ae37ce86bbee8c7f4d9376dca826c8492fa34 /src/soc/amd | |
| parent | e78ea98bb28b276a20ec50251e6a1dde01295c35 (diff) | |
soc/amd/genoa/chipset.cb: enable dummy functions
Enable the dummy function 0 that don't have an alias in the chipset
devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I607245c587a544007fd714f64901cbb50014612f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/genoa/chipset.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 1e90eb58fc..60918e9bf1 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -43,7 +43,7 @@ chip soc/amd/genoa device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 - device pci 0.0 off end # Dummy PCIe function + device pci 0.0 on end # Dummy PCIe function device pci 0.1 off end device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB @@ -107,7 +107,7 @@ chip soc/amd/genoa device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_1_a off - device pci 0.0 off end # Dummy PCIe function + device pci 0.0 on end # Dummy PCIe function device pci 0.1 off end #SDXI end end @@ -148,7 +148,7 @@ chip soc/amd/genoa device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_2_a off - device pci 0.0 off end # Dummy PCIe function + device pci 0.0 on end # Dummy PCIe function device pci 0.1 off end end end @@ -193,7 +193,7 @@ chip soc/amd/genoa device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_3_a off - device pci 0.0 off end # Dummy PCIe function + device pci 0.0 on end # Dummy PCIe function device pci 0.1 off end #SDXI device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB |