diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-08-03 20:09:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-03 15:51:37 +0000 |
| commit | 4b027690b658173719d3d24e43415e68650c26e7 (patch) | |
| tree | ebdc61b9905a8d9ad17f75ddf7ab470cb5fe7479 /src/soc/amd | |
| parent | 99c4a29cdc13418b05945af05dae635c1058c0f3 (diff) | |
soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/gpio_banks/Kconfig | 13 | ||||
| -rw-r--r-- | src/soc/amd/common/block/gpio_banks/gpio.c | 5 |
2 files changed, 16 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig index 1efb1db643..0a1bffee81 100644 --- a/src/soc/amd/common/block/gpio_banks/Kconfig +++ b/src/soc/amd/common/block/gpio_banks/Kconfig @@ -5,3 +5,16 @@ config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS Select this option to use the newer style banks of GPIO signals. These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio base. + +if SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + +config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE + bool + help + Select this option when selecting the GPIO bank support from AMD + chipsets outside the soc/ subtree that only support a subset of the + features available on the chipsets inside the soc/ subtree. When this + option is selected, no SMI or SCI event can be configured by the GPIO + code. + +endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 8f84cb67fc..b3c1ac1b72 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -171,8 +171,9 @@ static void set_single_gpio(const struct soc_amd_gpio *g) static const struct soc_amd_event *gev_tbl; static size_t gev_items; int gevent_num; - const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && - ENV_SEPARATE_VERSTAGE); + const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + ENV_SEPARATE_VERSTAGE) || + CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE)); set_gpio_mux(g->gpio, g->function); |