diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-02-06 16:55:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-23 15:13:37 +0000 |
| commit | 0d19289e840f9c711f50a74437d1b3856222db03 (patch) | |
| tree | ca4e8ce2d51dfa9d10deceb28393a28c061a0952 /src/soc/amd | |
| parent | a138cfb422109018ba35c8f5d82621717eaf0611 (diff) | |
arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/acpi/ivrs.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/root_complex/ioapic.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index bd52d7ca6f..74c5c39b52 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -16,7 +16,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> -static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base, +static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, uintptr_t ioapic_base, uint16_t src_devid, uint8_t dte_setting) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -182,7 +182,7 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev) res = probe_resource(dev, IOMMU_IOAPIC_IDX); if (res) { /* Describe IOAPIC associated with the IOMMU */ - current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, + current = acpi_fill_ivrs_ioapic(current, (uintptr_t)res->base, PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0); } @@ -191,7 +191,7 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev) /* Describe HPET */ current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); /* Describe FCH IOAPICs */ - current = acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, + current = acpi_fill_ivrs_ioapic(current, IO_APIC_ADDR, SMBUS_DEVFN, dte_setting); } diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index a90fc3e65c..2392d5f3e8 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -45,7 +45,7 @@ void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) static void fch_ioapic_init(void) { fch_enable_ioapic_decode(); - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); } static void lpc_init(struct device *dev) diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c index cdeb53239b..e183428ca5 100644 --- a/src/soc/amd/common/block/root_complex/ioapic.c +++ b/src/soc/amd/common/block/root_complex/ioapic.c @@ -13,5 +13,5 @@ void amd_pci_domain_init(struct device *domain) if (!res) return; - register_new_ioapic((void *)(uintptr_t)res->base); + register_new_ioapic((uintptr_t)res->base); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a92c3b506d..b51601ba02 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -73,7 +73,7 @@ static void set_resources(struct device *dev) static void northbridge_init(struct device *dev) { - register_new_ioapic((u8 *)IO_APIC2_ADDR); + register_new_ioapic(IO_APIC2_ADDR); } /* Used by \_SB.PCI0._CRS */ |