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authorFelix Held <felix-coreboot@felixheld.de>2021-02-03 21:38:14 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-05 22:05:59 +0000
commit7e703d77b2cb2189863d2a2e87f7de2913e20307 (patch)
tree2667898e7a0ab41ad613bf26129e03b071513592 /src/soc/amd
parent757d645cb069f1759303467efb9753fcdd847da4 (diff)
soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from the reference code, but not the PPR. I've submitted a change request for the PPR, so this mismatch might go away in the future. The case for HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends up being identical to the function in soc/amd/picasso, I'll move it to the common AMD SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/fch.c29
-rw-r--r--src/soc/amd/cezanne/include/soc/iomap.h10
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h30
3 files changed, 69 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index f853ecee93..5fb4f0ab98 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -1,9 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/acpimmio.h>
+#include <assert.h>
+#include <soc/iomap.h>
#include <soc/southbridge.h>
+static void fch_init_acpi_ports(void)
+{
+ /* We use some of these ports in SMM regardless of whether or not
+ * ACPI tables are generated. Enable these ports indiscriminately.
+ */
+
+ pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
+ pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
+ pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
+ pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
+
+ if (CONFIG(HAVE_SMI_HANDLER)) {
+ /* TODO: add code for SMI handler case */
+ dead_code();
+ } else {
+ pm_write16(PM_ACPI_SMI_CMD, 0);
+ }
+
+ /* Decode ACPI registers and enable standard features */
+ pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
+ PM_ACPI_GLOBAL_EN |
+ PM_ACPI_RTC_EN_EN |
+ PM_ACPI_TIMER_EN_EN);
+}
+
void fch_init(void *chip_info)
{
+ fch_init_acpi_ports();
}
void fch_final(void *chip_info)
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 20f70371f0..01b06479d8 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -16,6 +16,16 @@
/* I/O Ranges */
#define NCP_ERR 0x00f0
+#define ACPI_IO_BASE 0x0400
+#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)
+#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00)
+#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
+#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
+#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
+#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
+#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
+#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
+#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)
#define SMB_BASE_ADDR 0x0b00
#endif /* AMD_CEZANNE_IOMAP_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index a38d706f23..8623063140 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -8,7 +8,37 @@
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD (1 << 1)
+#define PM_EVT_BLK 0x60
+#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
+#define PCIEXPWAK_STS BIT(14)
+#define RTC_STS BIT(10)
+#define PWRBTN_STS BIT(8)
+#define GBL_STS BIT(5)
+#define BM_STS BIT(4)
+#define TIMER_STS BIT(0)
+#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
+#define RTC_EN BIT(10)
+#define PWRBTN_EN BIT(8)
+#define GBL_EN BIT(5)
+#define TIMER_STS BIT(0)
+#define PM1_CNT_BLK 0x62
+#define PM_TMR_BLK 0x64
+#define PM_GPE0_BLK 0x68
#define PM_ACPI_SMI_CMD 0x6a
+#define PM_ACPI_CONF 0x74
+#define PM_ACPI_DECODE_STD BIT(0)
+#define PM_ACPI_GLOBAL_EN BIT(1)
+#define PM_ACPI_RTC_EN_EN BIT(2)
+#define PM_ACPI_TIMER_EN_EN BIT(4)
+#define PM_ACPI_MASK_ARB_DIS BIT(6)
+#define PM_ACPI_BIOS_RLS BIT(7)
+#define PM_ACPI_PWRBTNEN_EN BIT(8)
+#define PM_ACPI_REDUCED_HW_EN BIT(9)
+#define PM_ACPI_BLOCK_PCIE_PME BIT(24)
+#define PM_ACPI_PCIE_WAK_MASK BIT(25)
+#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
+#define PM_ACPI_NB_PME_GEVENT BIT(28)
+#define PM_ACPI_RTC_WAKE_EN BIT(29)
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */