diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-11-30 15:50:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-04 10:21:42 +0000 |
| commit | 31218a4259708233c17fa8b09fa9d9c06ea1f2ad (patch) | |
| tree | a1d32df5213f557c61430bc341da1b64aa7f7c4d /src/soc/amd | |
| parent | 37cae540343d8f02258c3209f90114e7189753e2 (diff) | |
drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index bc514561ac..1391536464 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -92,7 +92,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *mcfg = &mupd->FspmConfig; const struct soc_amd_picasso_config *config = config_of_soc(); - mupd->FspmArchUpd.NvsBufferPtr = soc_fill_mrc_cache(); + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_mrc_cache(); mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; |