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authorRaul E Rangel <rrangel@chromium.org>2020-06-29 14:21:40 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-07-06 06:08:55 +0000
commit30d7b54742a7deb32a41110944c8c6235c0c8056 (patch)
treeb74925823f1dea3c8fbd60ec971a1815fe0082c0 /src/soc/amd
parente927d9b3adc9c5a4e4cc6757949f626458a80e68 (diff)
soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned
The bootblock must be 16-bit aligned for it to boot. BUG=b:159081993 TEST=Made sure trembyle still compiles. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/picasso/memlayout.ld1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld
index a82e303dad..6f43ba18af 100644
--- a/src/soc/amd/picasso/memlayout.ld
+++ b/src/soc/amd/picasso/memlayout.ld
@@ -81,6 +81,7 @@ SECTIONS
FMAP_CACHE(., FMAP_SIZE)
_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
+ _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)