diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2017-11-20 12:30:32 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-22 18:28:29 +0000 |
| commit | 2983c708155466d88776338b3a7faec9f80f0134 (patch) | |
| tree | 75341bbfdcc37f1a2b91d15b952aaf16b056a5bf /src/soc/amd | |
| parent | db7b8afc912d28cc368b89f86435f2c8a6e11cf1 (diff) | |
Create SOC description file soc.asl
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.
Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.
Affected boards: amd/gardenia and google/kahlee.
BUG=b:69368752
Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_fch.asl (renamed from src/soc/amd/stoneyridge/acpi/soc_fch.asl) | 0 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl (renamed from src/soc/amd/stoneyridge/acpi/fch.asl) | 0 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/soc.asl | 28 |
3 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/soc_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 9bf7decb49..9bf7decb49 100644 --- a/src/soc/amd/stoneyridge/acpi/soc_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6dcafe6faf..6dcafe6faf 100644 --- a/src/soc/amd/stoneyridge/acpi/fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl new file mode 100644 index 0000000000..d7772948ef --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(PCI0) { + /* Describe the AMD Northbridge */ + #include "northbridge.asl" + + /* Describe the AMD Fusion Controller Hub */ + #include "sb_pci0_fch.asl" +} + +/* Describe PCI INT[A-H] for the Southbridge */ +#include "pci_int.asl" + +/* Describe the devices in the Southbridge */ +#include "sb_fch.asl" |