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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-09-27 14:45:26 -0600
committerMartin Roth <martinroth@google.com>2017-10-02 22:31:14 +0000
commitf039a0befc9072c4e346f084c2a40dc8fd6de9fe (patch)
treed27b845a6412b2e431f7cc8b7771750ffa7418e2 /src/soc/amd/stoneyridge
parent36a2356fb1bb85468de1d9e191df890c46ff3861 (diff)
amd/stoneyridge: Add PM defintions to southbridge.h
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 80fcf87558..ebfee2499e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -41,6 +41,9 @@
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
+#define PM_PCI_CTRL 0x08
+#define FORCE_SLPSTATE_RETRY BIT(25)
+#define FORCE_STPCLK_RETRY BIT(24)
#define PM_ACPI_MMIO_EN 0x24
#define PM_SERIRQ_CONF 0x54
#define PM_EVT_BLK 0x60
@@ -50,6 +53,8 @@
#define PM_GPE0_BLK 0x68
#define PM_ACPI_SMI_CMD 0x6a
#define PM_ACPI_CONF 0x74
+#define PM_RST_CTRL1 0xbe
+#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_PMIO_DEBUG 0xd2
#define PM_MANUAL_RESET 0xd3
#define PM_HUD_SD_FLASH_CTRL 0xe7