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authorMartin Roth <gaumless@gmail.com>2022-10-29 13:31:54 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-11-04 01:00:27 +0000
commitbcb610a5595f7ff99129dfbaff9c6b4e1b5c3584 (patch)
treefd9197d90effa73f4b95bfb45804179db8034981 /src/soc/amd/stoneyridge
parentb6877e401a8686ac6dfcebb1184ebdfabad6f3e6 (diff)
soc/amd: Specify memory types supported by each chip
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 53b986e68a..01800c1414 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -18,6 +18,10 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_CF9_RESET
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
+ select NO_DDR5
+ select NO_DDR3
+ select NO_DDR2
+ select NO_LPDDR4
select PARALLEL_MP_AP_WORK
select RTC
select SOC_AMD_PI
@@ -45,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_UART
select SSE2
select TSC_SYNC_LFENCE
+ select USE_DDR4
select X86_AMD_FIXED_MTRRS
config AMD_APU_STONEYRIDGE