diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-05 16:08:51 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-12 15:15:10 +0000 |
| commit | 8db8432cf5851d69550411716603dd7947a84a7c (patch) | |
| tree | 2de2eba7ffabe4690b9c47ce57dc053144d2ca0b /src/soc/amd/stoneyridge | |
| parent | 1548458efd6b6065ea39524936afcbb7663ff33f (diff) | |
amd/stoneyridge: Clarify XHCI_PM register definitions
Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d4af8a1554..ce3660be3c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -279,27 +279,26 @@ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) +/* XHCI_PM Registers: 0xfed81c00 */ #define XHCI_PM_INDIRECT_INDEX 0x48 #define XHCI_PM_INDIRECT_DATA 0x4c #define XHCI_OVER_CURRENT_CONTROL 0x30 -#define EHCI_OVER_CURRENT_CONTROL 0x70 - -#define USB_OC0 0 -#define USB_OC1 1 -#define USB_OC2 2 -#define USB_OC3 3 -#define USB_OC4 4 -#define USB_OC5 5 -#define USB_OC6 6 -#define USB_OC7 7 -#define USB_OC_DISABLE 0xf -#define USB_OC_DISABLE_ALL 0xffff - -#define OC_PORT0_SHIFT 0 -#define OC_PORT1_SHIFT 4 -#define OC_PORT2_SHIFT 8 -#define OC_PORT3_SHIFT 12 +#define USB_OC0 0 +#define USB_OC1 1 +#define USB_OC2 2 +#define USB_OC3 3 +#define USB_OC4 4 +#define USB_OC5 5 +#define USB_OC6 6 +#define USB_OC7 7 +#define USB_OC_DISABLE 0xf +#define USB_OC_DISABLE_ALL 0xffff +#define OC_PORT0_SHIFT 0 +#define OC_PORT1_SHIFT 4 +#define OC_PORT2_SHIFT 8 +#define OC_PORT3_SHIFT 12 +#define EHCI_OVER_CURRENT_CONTROL 0x70 #define EHCI_HUB_CONFIG4 0x90 #define DEBUG_PORT_SELECT_SHIFT 16 #define DEBUG_PORT_ENABLE BIT(18) |