diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 01:06:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-07 19:38:33 +0000 |
| commit | dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32 (patch) | |
| tree | b5e181bbec41868647265e453fa08582655e7135 /src/soc/amd/stoneyridge | |
| parent | 2f8228d3c942638bc742cb076fb1204044424d64 (diff) | |
soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 2 |
2 files changed, 1 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index baf3f4e9df..b400e1b841 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -250,13 +250,6 @@ config SERIRQ_CONTINUOUS_MODE Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode. -config STONEYRIDGE_ACPI_IO_BASE - hex - default 0x400 - help - Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL hex diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 92d99e4c36..d8befbe873 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -27,7 +27,7 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ |