summaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-22 06:27:45 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-01-19 21:07:08 +0000
commitb64cdebd2debf1707ed4dfc3e7240014e7f1cf7b (patch)
tree76411f57d087c9036df695cf2a1e0df3aeef921f /src/soc/amd/stoneyridge
parentf1e25b1e35c1ab5c34c122d97e4a49257cb09aa2 (diff)
soc/amd/stoneyridge: Add struct chipset_state
Struct will be synced with picasso with followups. Change-Id: I5f460cc3849bf1fad1f6da61169893488ccb2b40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48855 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/acpi.h5
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c11
2 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index 19f0c81136..1430478c43 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -4,6 +4,7 @@
#define AMD_STONEYRIDGE_ACPI_H
#include <acpi/acpi.h>
+#include <amdblocks/acpi.h>
#if CONFIG(STONEYRIDGE_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
@@ -16,4 +17,8 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
const char *soc_acpi_name(const struct device *dev);
+struct chipset_state {
+ struct acpi_pm_gpe_state gpe_state;
+};
+
#endif /* AMD_STONEYRIDGE_ACPI_H */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 3aecbb4758..1a1dc8ef9f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -25,6 +25,7 @@
#include <delay.h>
#include <soc/pci_devs.h>
#include <agesa_headers.h>
+#include <soc/acpi.h>
#include <soc/nvs.h>
#include <types.h>
@@ -403,27 +404,27 @@ static void sb_init_acpi_ports(void)
static void set_nvs_sws(void *unused)
{
- struct acpi_pm_gpe_state *state;
+ struct chipset_state *state;
state = cbmem_find(CBMEM_ID_POWER_STATE);
if (state == NULL)
return;
- pm_fill_gnvs(state);
+ pm_fill_gnvs(&state->gpe_state);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
void southbridge_init(void *chip_info)
{
- struct acpi_pm_gpe_state *state;
+ struct chipset_state *state;
sb_init_acpi_ports();
state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
if (state) {
- acpi_fill_pm_gpe_state(state);
- acpi_pm_gpe_add_events_print_events(state);
+ acpi_fill_pm_gpe_state(&state->gpe_state);
+ acpi_pm_gpe_add_events_print_events(&state->gpe_state);
}
acpi_clear_pm_gpe_status();