diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-05-31 09:59:14 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-16 08:04:48 +0000 |
| commit | 87e6796a90d1f1cadd5b4981d6f45388de96bd42 (patch) | |
| tree | dabe0cc0ad18364ab7ed60df42cc86116b79753e /src/soc/amd/stoneyridge | |
| parent | b264c5ce10f6c4a2f46454b72de25048e0ef21fb (diff) | |
soc/amd: Replace enable_smi_generation()
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smi.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/smi.c | 2 |
3 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9189cfb8c1..c898ff7f93 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -90,7 +90,7 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = relocation_handler, - .post_mp_init = enable_smi_generation, + .post_mp_init = global_smi_enable, }; void mp_init_cpus(struct bus *cpu_bus) diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 9268341f99..a58488ba3c 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -220,6 +220,4 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -void enable_smi_generation(void); - #endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 17836464b2..a3473aafc5 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -16,7 +16,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) } /** Set the EOS bit and enable SMI generation from southbridge */ -void enable_smi_generation(void) +void global_smi_enable(void) { uint32_t reg = smi_read32(SMI_REG_SMITRIG0); reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ |