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| author | Furquan Shaikh <furquan@google.com> | 2017-12-20 11:06:19 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-12-23 09:17:54 +0000 |
| commit | 58a8c779b3ce826b376ac59198e9a97ceaf03767 (patch) | |
| tree | 0e002c197477d9d295a450c5a8b9f3a964f9f2a1 /src/soc/amd/stoneyridge | |
| parent | 261b893b7c82839e997c4310e5214a4388b3a62c (diff) | |
soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Even though kaby lake and cannon lake are using the same GSPI
controller, bit meanings (for polarity and state) in SPI_CS_CONTROL
register are significantly different. This change provides a new
Kconfig option that can be selected by SoCs using these new bit
definitions of SPI_CS_CONTROL. Common code takes care of setting the
right value for polarity and state field depending upon the version
selected by SoC.
BUG=b:70628116
Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/amd/stoneyridge')
0 files changed, 0 insertions, 0 deletions