soc/amd/stoneyridge: consolidate addresses in iomap.h

Take the existing scattered around address space defines
and put them in iomap.h.

Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

3 files changed, 32 insertions, 35 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index d0c3f3e9d4..af3d0cbeb8 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -17,6 +17,35 @@
 #ifndef __SOC_STONEYRIDGE_IOMAP_H__
 #define __SOC_STONEYRIDGE_IOMAP_H__
 
-#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul
+/* MMIO Ranges */
+#define SPI_BASE_ADDRESS		0xfec10000
+#define IO_APIC2_ADDR			0xfec20000
+
+#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE)
+#error HPET address override is not allowed and must be fixed at 0xfed00000
+#endif
+#define HPET_BASE_ADDRESS		0xfed00000
+
+/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */
+#define AMD_SB_ACPI_MMIO_ADDR		0xfed80000
+#define APU_SMI_BASE			0xfed80200
+#define PM_MMIO_BASE			0xfed80300
+#define APU_UART0_BASE			0xfedc6000
+#define APU_UART1_BASE			0xfedc8000
+
+#define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
+
+/* I/O Ranges */
+#define ACPI_SMI_CTL_PORT		0xb2
+#define STONEYRIDGE_ACPI_IO_BASE	CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define  ACPI_PM_EVT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define  ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define  ACPI_CPU_CONTROL	(STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
+#define  ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define  ACPI_PM_TMR_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define SMB_BASE_ADDR			0xb00
+#define AB_INDX				0xcd8
+#define AB_DATA				(AB_INDX+4)
+#define SYS_RESET			0xcf9
 
 #endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h
index 1ec4e48277..db3e9b2e5f 100644
--- a/src/soc/amd/stoneyridge/include/soc/smbus.h
+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h
@@ -17,6 +17,7 @@
 #define __STONEYRIDGE_SMBUS_H__
 
 #include <stdint.h>
+#include <soc/iomap.h>
 
 #define SMBHSTSTAT			0x0
 #define   SMBHST_STAT_FAILED		0x10
@@ -59,8 +60,6 @@
 #define SMBSLVDAT			0xc
 #define SMBTIMING			0xe
 
-#define SMB_BASE_ADDR			0xb00
-
 #define AX_INDXC			0
 #define AX_INDXP			2
 #define AXCFG				4
@@ -68,9 +67,6 @@
 #define RC_INDXC			1
 #define RC_INDXP			3
 
-#define AB_INDX				0xcd8
-#define AB_DATA				(AB_INDX+4)
-
 /*
  * Between 1-10 seconds, We should never timeout normally
  * Longer than this is just painful when a timeout condition occurs.
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 8630ea92a7..19aaa4cbb8 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -21,24 +21,9 @@
 #include <types.h>
 #include <device/pci_ids.h>
 #include <device/device.h>
+#include <soc/iomap.h>
 #include "chip.h"
 
-#define IO_APIC2_ADDR			0xfec20000
-
-#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE)
-#error HPET address override is not allowed and must be fixed at 0xfed00000
-#endif
-#define HPET_BASE_ADDRESS		0xfed00000
-
-/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */
-
-#define APU_SMI_BASE			0xfed80200
-
-#define PM_MMIO_BASE			0xfed80300
-
-#define APU_UART0_BASE			0xfedc6000
-#define APU_UART1_BASE			0xfedc8000
-
 /* Power management index/data registers */
 #define BIOSRAM_INDEX			0xcd4
 #define BIOSRAM_DATA			0xcd5
@@ -82,16 +67,6 @@
 #define   PM_LPC_A20_EN			BIT(1)
 #define   PM_LPC_ENABLE			BIT(0)
 
-#define SYS_RESET			0xcf9
-
-#define STONEYRIDGE_ACPI_IO_BASE	CONFIG_STONEYRIDGE_ACPI_IO_BASE
-#define ACPI_PM_EVT_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PM_TMR_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTROL	(STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
-
-#define ACPI_SMI_CTL_PORT		0xb2
 #define ACPI_SMI_CMD_CST_CONTROL	0xde
 #define ACPI_SMI_CMD_PST_CONTROL	0xad
 #define ACPI_SMI_CMD_DISABLE		0xbe
@@ -107,7 +82,6 @@
 #define   SPI_ROM_ENABLE		BIT(1)
 #define   SPI_ROM_ALT_ENABLE		BIT(0)
 #define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define   SPI_BASE_ADDRESS		0xfec10000
 
 #define LPC_PCI_CONTROL			0x40
 #define   LEGACY_DMA_EN			BIT(2)
@@ -239,8 +213,6 @@
 
 #define FCH_MISC_REG40_OSCOUT1_EN	BIT(2)
 
-#define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
-
 static inline int sb_sata_enable(void)
 {
 	/* True if IDE or AHCI. */