diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-08 02:07:18 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 02:11:53 +0000 |
| commit | 37609852f7955bd2496a3555d215c03d2c145938 (patch) | |
| tree | 79134f1a6dd07b64ccaee026516bd70481d92c05 /src/soc/amd/stoneyridge | |
| parent | 20a4874445dfc52b4721b01246d86e1114165b1b (diff) | |
soc/amd: factor out functionality to print last reset source
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 54 |
2 files changed, 1 insertions, 54 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index a4f43ec112..c627f7ec7c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -72,7 +72,6 @@ #define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) -#define PM_RST_STATUS 0xc0 #define PM_PCIB_CFG 0xea #define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index ba23e90b58..4436e0ebf0 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -344,62 +344,10 @@ void bootblock_fch_early_init(void) enable_aoac_devices(); } -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static void sb_print_pmxc0_status(void) -{ - /* PMxC0 S5/Reset Status shows the source of previous reset. */ - uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); - - static const char *const pmxc0_status_bits[32] = { - [0] = "ThermalTrip", - [1] = "FourSecondPwrBtn", - [2] = "Shutdown", - [3] = "ThermalTripFromTemp", - [4] = "RemotePowerDownFromASF", - [5] = "ShutDownFan0", - [16] = "UserRst", - [17] = "SoftPciRst", - [18] = "DoInit", - [19] = "DoReset", - [20] = "DoFullReset", - [21] = "SleepReset", - [22] = "KbReset", - [23] = "LtReset", - [24] = "FailBootRst", - [25] = "WatchdogIssueReset", - [26] = "RemoteResetFromASF", - [27] = "SyncFlood", - [28] = "HangReset", - [29] = "EcWatchdogRst", - }; - - printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); - print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, - pmxc0_status_bits); - printk(BIOS_DEBUG, "\n"); -} - /* After console init */ void bootblock_fch_init(void) { - sb_print_pmxc0_status(); + fch_print_pmxc0_status(); } void sb_enable(struct device *dev) |