soc/amd/common: Add DRAM clear option to northbridge.c

AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.

Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.

Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 18 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index de6585e164..4623800848 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -24,6 +24,10 @@
 
 struct soc_amd_stoneyridge_config {
 	u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
+	enum {
+		DRAM_CONTENTS_KEEP,
+		DRAM_CONTENTS_CLEAR
+	} dram_clear_on_reset;
 };
 
 typedef struct soc_amd_stoneyridge_config config_t;
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index a152c1f399..9b22761f9e 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -111,3 +111,17 @@ asmlinkage void car_stage_entry(void)
 
 	post_code(0x50);  /* Should never see this post code. */
 }
+
+void SetMemParams(AMD_POST_PARAMS *PostParams)
+{
+	const struct soc_amd_stoneyridge_config *cfg;
+	const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n");
+		return;
+	}
+
+	cfg = dev->chip_info;
+	PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
+}