coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

16 files changed, 28 insertions, 28 deletions

diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index 018975f098..1027ae0294 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -59,7 +59,7 @@ AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData,
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
 
 		/* XHCI configuration */
-		if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
+		if (CONFIG(STONEYRIDGE_XHCI_ENABLE))
 			FchParams_env->Usb.Xhci0Enable = TRUE;
 		else
 			FchParams_env->Usb.Xhci0Enable = FALSE;
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 3d7d833a96..227fb70136 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -91,7 +91,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->preferred_pm_profile = FADT_PM_PROFILE;
 	fadt->sci_int = 9;		/* IRQ 09 - ACPI SCI */
 
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		fadt->smi_cmd = APM_CNT;
 		fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
 		fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
@@ -268,10 +268,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
 	/* Clear out GNVS. */
 	memset(gnvs, 0, sizeof(*gnvs));
 
-	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
+	if (CONFIG(CONSOLE_CBMEM))
 		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+	if (CONFIG(CHROMEOS)) {
 		/* Initialize Verified Boot data */
 		chromeos_init_chromeos_acpi(&gnvs->chromeos);
 		gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl
index 0b297fa1f5..d4aabdb7af 100644
--- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl
+++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl
@@ -16,7 +16,7 @@
 
 /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
 Name(SSFG, 0x09)
-If (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
+If (CONFIG(HAVE_ACPI_RESUME)) {
 	Store(0x0D, SSFG)
 }
 
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 37e22ac73d..9239030d6c 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -108,7 +108,7 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
-	if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
+	if (CONFIG(STONEYRIDGE_UART))
 		assert(CONFIG_UART_FOR_CONSOLE >= 0
 					&& CONFIG_UART_FOR_CONSOLE <= 1);
 
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index a29c56c9da..1bd8cbf2f8 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -159,7 +159,7 @@ static void earliest_ramstage(void *unused)
 			romstage_handoff_is_resume();
 	if (!s3_resume) {
 		post_code(0x46);
-		if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
+		if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 			psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
 
 		post_code(0x47);
diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c
index 45e659504b..6572e1a201 100644
--- a/src/soc/amd/stoneyridge/finalize.c
+++ b/src/soc/amd/stoneyridge/finalize.c
@@ -29,7 +29,7 @@ static void per_core_finalize(void *unused)
 	if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */
 		return;
 
-	if (IS_ENABLED(CONFIG_SMM_TSEG)) {
+	if (CONFIG(SMM_TSEG)) {
 		mask = rdmsr(SMM_MASK_MSR);
 		mask.lo |= SMM_TSEG_VALID;
 		wrmsr(SMM_MASK_MSR, mask);
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index 3212ec7cf7..15a41edce6 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -20,7 +20,7 @@
 
 #include <arch/acpi.h>
 
-#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
+#if CONFIG(STONEYRIDGE_LEGACY_FREE)
 	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
 #else
 	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index b1010142ef..613dd044f6 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -27,7 +27,7 @@
 #define I2C_DEVICE_SIZE		0x00001000
 #define I2C_DEVICE_COUNT	4
 
-#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE)
+#if CONFIG(HPET_ADDRESS_OVERRIDE)
 #error HPET address override is not allowed and must be fixed at 0xfed00000
 #endif
 #define HPET_BASE_ADDRESS		0xfed00000
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 68b5b08f1f..e3475eebcb 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -98,7 +98,7 @@ static void lpc_init(struct device *dev)
 
 	/* Set up SERIRQ, enable continuous mode */
 	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
-	if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
+	if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
 		byte |= PM_SERIRQ_MODE;
 
 	pm_write8(PM_SERIRQ_CONF, byte);
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index eddaba4951..8a875d9206 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -199,7 +199,7 @@ void check_mca(void)
 						i, mci.cmask.hi, mci.cmask.lo);
 
 				mci.bank = i;
-				if (IS_ENABLED(CONFIG_ACPI_BERT)
+				if (CONFIG(ACPI_BERT)
 						&& mca_valid(mci.sts))
 					build_bert_mca_error(&mci);
 			}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 6c2637f26b..927cce0c1f 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -237,7 +237,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
 	current += hest->header.length;
 
 	/* BERT */
-	if (IS_ENABLED(CONFIG_ACPI_BERT) && bert_errors_present()) {
+	if (CONFIG(ACPI_BERT) && bert_errors_present()) {
 		/* Skip the table if no errors are present.  ACPI driver reports
 		 * a table with a 0-length region:
 		 *   BERT: [Firmware Bug]: table invalid.
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index d805683f71..edd5c2394e 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -36,7 +36,7 @@ uintptr_t restore_top_of_low_cacheable(void)
 	return biosram_read32(BIOSRAM_CBMEM_TOP);
 }
 
-#if IS_ENABLED(CONFIG_ACPI_BERT)
+#if CONFIG(ACPI_BERT)
  #if CONFIG_SMM_TSEG_SIZE == 0x0
   #define BERT_REGION_MAX_SIZE 0x100000
  #else
@@ -49,7 +49,7 @@ uintptr_t restore_top_of_low_cacheable(void)
 
 void bert_reserved_region(void **start, size_t *size)
 {
-	if (IS_ENABLED(CONFIG_ACPI_BERT))
+	if (CONFIG(ACPI_BERT))
 		*start = cbmem_top();
 	else
 		start = NULL;
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 42f6f8a758..f2263b7aa9 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -93,7 +93,7 @@ asmlinkage void car_stage_entry(void)
 
 	console_init();
 
-	if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
+	if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 		load_smu_fw1();
 
 	mainboard_romstage_entry(s3_resume);
@@ -132,7 +132,7 @@ asmlinkage void car_stage_entry(void)
 		msr_t sys_cfg = rdmsr(SYSCFG_MSR);
 		sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
 		wrmsr(SYSCFG_MSR, sys_cfg);
-		if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT))
+		if (CONFIG(ELOG_BOOT_COUNT))
 			boot_count_increment();
 	} else {
 		printk(BIOS_INFO, "S3 detected\n");
@@ -192,7 +192,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
 		/* In case of a BIOS error, only attempt to set UMA. */
-		PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ?
+		PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
 					UMA_AUTO : UMA_NONE;
 		return;
 	}
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index 657ff493dc..c053d909f7 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -103,7 +103,7 @@ static void sb_apmc_smi_handler(void)
 		acpi_write32(MMIO_ACPI_PM1_CNT_BLK, reg32);
 		break;
 	case APM_CNT_ELOG_GSMI:
-		if (IS_ENABLED(CONFIG_ELOG_GSMI))
+		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi();
 		break;
 	}
@@ -156,7 +156,7 @@ static void sb_slp_typ_handler(void)
 
 	if (slp_typ >= ACPI_S3) {
 		/* Sleep Type Elog S3, S4, and S5 entry */
-		if (IS_ENABLED(CONFIG_ELOG_GSMI))
+		if (CONFIG(ELOG_GSMI))
 			elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 
 		wbinvd();
@@ -183,7 +183,7 @@ static void sb_slp_typ_handler(void)
 		 * it and continue normal path. S3 will fail and the wake event
 		 * becomes a SCI.
 		 */
-		if (IS_ENABLED(CONFIG_ELOG_GSMI)) {
+		if (CONFIG(ELOG_GSMI)) {
 			reg16 = acpi_read16(MMIO_ACPI_PM1_EN);
 			reg16 &= acpi_read16(MMIO_ACPI_PM1_STS);
 			if (reg16)
@@ -197,7 +197,7 @@ static void sb_slp_typ_handler(void)
 				elog_add_extended_event(
 						ELOG_SLEEP_PENDING_GPE0_WAKE,
 						reg32);
-		} /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */
+		} /* if (CONFIG(ELOG_GSMI)) */
 
 		/*
 		 * An IO cycle is required to trigger the STPCLK/STPGNT
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 069fc7879c..2f32c5c86e 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -76,7 +76,7 @@ static inline int sb_ide_enable(void)
 void SetFchResetParams(FCH_RESET_INTERFACE *params)
 {
 	const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
-	params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
+	params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE);
 	if (dev && dev->enabled) {
 		params->SataEnable = sb_sata_enable();
 		params->IdeEnable = sb_ide_enable();
@@ -553,7 +553,7 @@ static void sb_lpc_early_setup(void)
 	dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;
 	pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
 
-	if (IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)) {
+	if (CONFIG(STONEYRIDGE_LEGACY_FREE)) {
 		/* Decode SIOs at 2E/2F and 4E/4F */
 		dword = pci_read_config32(SOC_LPC_DEV,
 						LPC_IO_OR_MEM_DECODE_ENABLE);
@@ -742,7 +742,7 @@ static void sb_init_acpi_ports(void)
 	/* CpuControl is in \_PR.CP00, 6 bytes */
 	pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
 
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		/* APMC - SMI Command Port */
 		pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
 		configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
@@ -804,7 +804,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts)
 
 static void sb_log_pm1_status(uint16_t pm1_sts)
 {
-	if (!IS_ENABLED(CONFIG_ELOG))
+	if (!CONFIG(ELOG))
 		return;
 
 	if (pm1_sts & WAK_STS)
@@ -952,7 +952,7 @@ void southbridge_final(void *chip_info)
 {
 	uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
 
-	if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE))
+	if (CONFIG(MAINBOARD_POWER_RESTORE))
 		restored_power = PM_RESTORE_S0_IF_PREV_S0;
 	pm_write8(PM_RTC_SHADOW, restored_power);
 
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
index 409b9b1904..e6b1a36d16 100644
--- a/src/soc/amd/stoneyridge/spi.c
+++ b/src/soc/amd/stoneyridge/spi.c
@@ -29,7 +29,7 @@
 #include <soc/southbridge.h>
 #include <soc/pci_devs.h>
 
-#define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH)
 
 static uintptr_t spibar;