diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-29 07:30:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:54:39 +0000 |
| commit | bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb (patch) | |
| tree | ab42496f77d4bf76f3f9f79eea16ddc92d8a5cd6 /src/soc/amd/stoneyridge | |
| parent | 11cac784ff788b4f0495758d7f5992e457ea552c (diff) | |
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index be40e2171c..973e6090c5 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -1,28 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <amdblocks/acpi.h> +#include <amdblocks/agesawrapper.h> +#include <amdblocks/agesawrapper_call.h> #include <amdblocks/biosram.h> -#include <device/pci_ops.h> +#include <amdblocks/psp.h> #include <arch/cpu.h> #include <arch/romstage.h> -#include <acpi/acpi.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> +#include <device/pci_ops.h> +#include <elog.h> #include <program_loading.h> +#include <romstage_common.h> #include <romstage_handoff.h> -#include <elog.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/psp.h> #include <stdint.h> #include "chip.h" @@ -47,8 +48,7 @@ static void bsp_agesa_call(void) set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ agesa_call(); } - -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -56,8 +56,6 @@ asmlinkage void car_stage_entry(void) int s3_resume = acpi_is_wakeup_s3(); int i; - console_init(); - soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); @@ -121,6 +119,7 @@ asmlinkage void car_stage_entry(void) post_code(0x44); prepare_and_run_postcar(); + die("failed to load postcar\n"); } void fill_postcar_frame(struct postcar_frame *pcf) |