soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK

Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build.  The .S files
are mostly duplicated code from the old cache_as_ram.inc file.

The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.

Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.  Drop the BIST check like other devices.

Move InitReset and InitEarly to bootblock.  These AGESA entry
points set some default settings, and release/recapture the
AP cores.  There are currently some early dependencies on
InitReset.  Future work should include:
 * Pull the necessary functionality from InitReset into bootblock
 * Move InitReset and InitEarly to car_stage_entry() and out of
   bootblock
   - Add a mechanism for the BSP to give the APs an address
     to call and skip most of bootblock and verstage (when
     available) (1)
   - Reunify BiosCallOuts.c and OemCustomize.c

(1) During the InitReset call, the BSP enables the APs by setting
    core enable bits in F18F0x1DC and APs begin fetching/executing
    from the reset vector.  The BSP waits for all APs to also
    reach InitReset, where they enter an endless loop.  The BSP
    sends a command to them to execute a HLT instruction and the
    BSP eventually returns from InitReset.  The goal would be to
    preserve this process but prevent APs from rerunning early
    code.

Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 163 insertions, 44 deletions

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 8d534cd6ac..aa694ef07b 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -40,10 +40,14 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_CONSTANT_RATE
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select TSC_SYNC_LFENCE
+	select COLLECT_TIMESTAMPS
 	select SOC_AMD_PI
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK
 	select SOC_AMD_COMMON_BLOCK_PSP
+	select SOC_AMD_COMMON_BLOCK_CAR
+	select C_ENVIRONMENT_BOOTBLOCK
+	select BOOTBLOCK_CONSOLE
 
 config UDELAY_LAPIC_FIXED_FSB
 	int
@@ -61,6 +65,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config DCACHE_BSP_STACK_SIZE
+	depends on C_ENVIRONMENT_BOOTBLOCK
+	hex
+	default 0x4000
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages.
+
 config CPU_ADDR_BITS
 	int
 	default 48
@@ -124,10 +136,6 @@ config RAMBASE
 	hex
 	default 0x200000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "soc/amd/stoneyridge/bootblock/bootblock.c"
-
 config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 97d402e0a2..4997098267 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -37,6 +37,13 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 subdirs-y += ../../../cpu/x86/smm
 
+bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
+bootblock-y += fixme.c
+bootblock-y += bootblock/bootblock.c
+bootblock-y += early_setup.c
+bootblock-y += tsc_freq.c
+
+romstage-y += romstage.c
 romstage-y += early_setup.c
 romstage-y += dimmSpd.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 8efe744384..473b118d11 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2017 Advanced Micro Devices
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,52 +15,49 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
-#include <device/pci_ids.h>
-#include <soc/pci_devs.h>
+#include <console/console.h>
+#include <smp/node.h>
+#include <bootblock_common.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
+#include <soc/hudson.h>
 
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The HUDSON power-on default is to map 512K ROM space.
- *
- */
-static void hudson_enable_rom(void)
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	u8 reg8;
-	pci_devfn_t dev;
+	/*
+	 * Call lib/bootblock.c main with BSP, shortcut for APs
+	 *  todo: rearchitect AGESA entry points to remove need
+	 *        to run amdinitreset, amdinitearly from bootblock.
+	 *        Remove AP shortcut.
+	 */
+	if (!boot_cpu())
+		bootblock_soc_early_init(); /* APs will not return */
 
-	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	bootblock_main_with_timestamp(base_timestamp);
+}
 
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+void bootblock_soc_early_init(void)
+{
+	amd_initmmio();
 
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	if (!boot_cpu())
+		bootblock_soc_init(); /* APs will not return */
 
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000
-					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	bootblock_fch_early_init();
+
+	post_code(0x90);
+	if (CONFIG_STONEYRIDGE_UART)
+		configure_hudson_uart();
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_soc_init(void)
 {
-	hudson_enable_rom();
+	u32 val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+
+	post_code(0x37);
+	AGESAWRAPPER(amdinitreset);
+
+	post_code(0x38);
+	AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */
 }
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index f1539eae52..c1a2978c0e 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -301,3 +301,51 @@ void hudson_tpm_decode_spi(void)
 	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
 							| ROUTE_TPM_2_SPI);
 }
+
+/*
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The HUDSON power-on default is to map 512K ROM space.
+ *
+ */
+void hudson_enable_rom(void)
+{
+	u8 reg8;
+	pci_devfn_t dev;
+
+	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+
+	/* Decode variable LPC ROM address ranges 1 and 2. */
+	reg8 = pci_io_read_config8(dev, 0x48);
+	reg8 |= (1 << 3) | (1 << 4);
+	pci_io_write_config8(dev, 0x48, reg8);
+
+	/* LPC ROM address range 1: */
+	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
+	pci_io_write_config16(dev, 0x68, 0x000e);
+	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+	pci_io_write_config16(dev, 0x6a, 0x000f);
+
+	/* LPC ROM address range 2: */
+	/*
+	 * Enable LPC ROM range start at:
+	 * 0xfff8(0000): 512KB
+	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
+	 */
+	pci_io_write_config16(dev, 0x6c, 0x10000
+					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	/* Enable LPC ROM range end at 0xffff(ffff). */
+	pci_io_write_config16(dev, 0x6e, 0xffff);
+}
+
+void bootblock_fch_early_init(void)
+{
+	hudson_enable_rom();
+	hudson_lpc_port80();
+	hudson_lpc_decode();
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h
index c69ab679e6..62d5a84395 100644
--- a/src/soc/amd/stoneyridge/include/soc/hudson.h
+++ b/src/soc/amd/stoneyridge/include/soc/hudson.h
@@ -179,6 +179,7 @@ static inline int hudson_ide_enable(void)
 					(CONFIG_STONEYRIDGE_SATA_MODE == 3);
 }
 
+void hudson_enable_rom(void);
 void configure_hudson_uart(void);
 void hudson_clk_output_48Mhz(void);
 void hudson_disable_4dw_burst(void);
@@ -201,5 +202,6 @@ void pm_write16(u8 reg, u16 value);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+void bootblock_fch_early_init(void);
 
 #endif /* STONEYRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index a87d66b845..e082a9d067 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -16,6 +16,7 @@
 #ifndef PI_STONEYRIDGE_NORTHBRIDGE_H
 #define PI_STONEYRIDGE_NORTHBRIDGE_H
 
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <device/device.h>
 
@@ -26,4 +27,7 @@ void domain_set_resources(device_t dev);
 void fam15_finalize(void *chip_info);
 void setup_uma_memory(void);
 
+/* todo: remove this when postcar stage is in place */
+asmlinkage void chipset_teardown_car(void);
+
 #endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
new file mode 100644
index 0000000000..1380fb7672
--- /dev/null
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
+#include <soc/northbridge.h>
+#include <soc/hudson.h>
+#include <amdblocks/psp.h>
+
+asmlinkage void car_stage_entry(void)
+{
+	console_init();
+
+	post_code(0x40);
+	AGESAWRAPPER(amdinitpost);
+
+	post_code(0x41);
+	psp_notify_dram();
+
+	post_code(0x42);
+	cbmem_initialize_empty();
+
+	/*
+	 * This writes contents to DRAM backing before teardown.
+	 * todo: move CAR teardown to postcar implementation and
+	 *       relocate amdinitenv to ramstage.
+	 */
+	chipset_teardown_car();
+
+	post_code(0x43);
+	AGESAWRAPPER(amdinitenv);
+
+	post_code(0x50);
+	run_ramstage();
+
+	post_code(0x54);  /* Should never see this post code. */
+}