diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-15 19:16:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-16 21:25:25 +0000 |
| commit | 3cf05b58e5a675c0dd7efd57ab0ae082279f4e55 (patch) | |
| tree | 1db424e5b0f0db34c13e93c319c982f067d912cf /src/soc/amd/stoneyridge | |
| parent | beaa8f895d67e7fdb45ef05a581d017dbd59ad9e (diff) | |
soc/amd/*/Kconfig: change ACPI_CPU_STRING to use hexadecimal CPU numbers
Both the AMD AGESA reference code and the default coreboot
ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so
change the ACPI_CPU_STRING format string in the both the Stoneyridge
Kconfig and the common non-CAR AMD SoC config Kconfig which covers all
other AMD SoCs in soc/amd. All platforms where the P state and C state
SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot
before it got replaced by native code, had at most 8 cores/threads, so
the mismatch never became apparent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f57111d863..1e35d766af 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -268,7 +268,7 @@ config SMM_MODULE_STACK_SIZE config ACPI_CPU_STRING string - default "P%03d" + default "P%03X" config ACPI_SSDT_PSD_INDEPENDENT default n |